XQ2V1000 Datasheet, PDF (33/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

R
Multiplier Blocks
QPro Virtex-II 1.5V Military QML Platform FPGAs
Multiplier Blocks
Multiplier Blocks
Figure 38: Multipliers (2-column, 4-column, and 6-column)
DS031_39_110403
Global Clock Multiplexer Buffers
Virtex-II devices have 16 clock input pins that can also be
used as regular user I/Os. Eight clock pads are on the top
edge of the device, in the middle of the array, and eight are
on the bottom edge, as illustrated in Figure 39.
The global clock multiplexer buffer represents the input to
dedicated low-skew clock tree distribution in Virtex-II
devices. Like the clock pads, eight global clock multiplexer
buffers are on the top edge of the device and eight are on
the bottom edge.
8 clock pads
Virtex-II
Device
8 clock pads
DS031_42_101000
Figure 39: Virtex-II Clock Pads
DS122 (v1.1) January 7, 2004
www.xilinx.com
33
Product Specification
1-800-255-7778