XQ2V1000 Datasheet, PDF (25/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

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QPro Virtex-II 1.5V Military QML Platform FPGAs
Sum of Products
Each Virtex-II slice has a dedicated OR gate named ORCY,
ORing together outputs from the slices carryout and the ORCY
from an adjacent slice. The ORCY gate with the dedicated
Sum of Products (SOP) chain are designed for implementing
large, flexible SOP chains. One input of each ORCY is con-
nected through the fast SOP chain to the output of the previous
ORCY in the same slice row. The second input is connected to
the output of the top MUXCY in the same slice, as shown in
Figure 26.
LUTs and MUXCYs can implement large AND gates or
other combinatorial logic functions. Figure 27 illustrates
LUT and MUXCY resources configured as a 16-input AND
gate.
ORCY
ORCY
4 _LUT
4 _LUT
4
MUXCY
Slice 1
4
MUXCY
LUT
LUT
MUXCY
Slice 3
MUXCY
4 _LUT
4 _LUT
ORCY
MUXCY
4 _LUT
Slice 1
MUXCY
4 _LUT
ORCY
SOP
MUXCY
Slice 3
MUXCY
4 _LUT
4 _LUT
4
MUXCY
Slice 0
4
MUXCY
V_CC
LUT
LUT
MUXCY
Slice 2
MUXCY
V_CC
CLB
4 _LUT
4 _LUT
MUXCY
Slice 0
MUXCY
V_CC
4 _LUT
4 _LUT
Figure 26: Horizontal Cascade Chain
MUXCY
Slice 2
MUXCY
V_CC
CLB
ds031_64_110300
OUT
4
LUT
4
LUT
MUXCY
0
1
“0”
Slice
MUXCY
0
1
“0”
16
AND OUT
4
LUT
4
LUT
MUXCY
0
1
“0”
Slice
MUXCY
0
1
VCC
DS031_41_110600
Figure 27: Wide-Input AND Gate (16 Inputs)
DS122 (v1.1) January 7, 2004
www.xilinx.com
25
Product Specification
1-800-255-7778