XQ2V1000 Datasheet, PDF (12/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

QPro Virtex-II 1.5V Military QML Platform FPGAs
R
and connected to device pins that serve groups of IOB
blocks, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.
Eight I/O banks result from dividing each edge of the FPGA
into two banks, as shown in Figure 8 and Figure 9. Each
bank has multiple V_CCO pins, all of which must be con-
nected to the same voltage. This voltage is determined by
the output standards in use.
Bank 0
Bank 1
Bank 5
Bank 4
ug002_c2_014_112900
Figure 8: Virtex-II I/O Banks: Top View for Wire-Bond
Packages (CS, FG, & BG)
Some input standards require a user-supplied threshold
voltage (V_REF), and certain user-I/O pins are automatically
configured as V_REF inputs. Approximately one in six of the
I/O pins in the bank assume this role.
Bank 1
Bank 0
Bank 4
Bank 5
ds031_66_112900
Figure 9: Virtex-II I/O Banks: Top View for Flip-Chip
Packages (FF & BF)
V_REF pins within a bank are interconnected internally, and
consequently only one V_REF voltage can be used within
each bank. However, for correct operation, all V_REF pins in
the bank must be connected to the external reference volt-
age source.
The V_CCO and the V_REF pins for each bank appear in the
device pinout tables. Within a given package, the number of
V_REF and V_CCO pins can vary depending on the size of
device. In larger devices, more I/O pins convert to V_REF
pins. Since these are always a superset of the V_REF pins
used for smaller devices, it is possible to design a PCB that
permits migration to a larger device if necessary.
All V_REF pins for the largest device anticipated must be con-
nected to the V_REF voltage and are not used for I/O. In
smaller devices, some V_CCO pins used in larger devices do
not connect within the package. These unconnected pins
can be left unconnected externally, or, if necessary, they can
be connected to V_CCO to permit migration to a larger device.
Rules for Combining I/O Standards in the Same Bank
The following rules must be obeyed to combine different
input, output, and bidirectional standards in the same bank:
1. Combining output standards only. Output standards
with the same output V_CCO requirement can be
combined in the same bank.
Compatible example:
SSTL2_I and LVDS_25_DCI outputs
Incompatible example:
SSTL2_I (output V_CCO = 2.5V) and
LVCMOS33 (output V_CCO = 3.3V) outputs
2. Combining input standards only. Input standards
with the same input V_CCO and input V_REF requirements
can be combined in the same bank.
Compatible example:
LVCMOS15 and HSTL_IV inputs
Incompatible example:
LVCMOS15 (input V_CCO = 1.5V) and
LVCMOS18 (input V_CCO = 1.8V) inputs
Incompatible example:
HSTL_I_DCI_18 (V_REF = 0.9V) and
HSTL_IV_DCI_18 (V_REF = 1.1V) inputs
3. Combining input standards and output standards.
Input standards and output standards with the same
input V_CCO and output V_CCO requirement can be
combined in the same bank.
Compatible example:
LVDS_25 output and HSTL_I input
Incompatible example:
LVDS_25 output (output V_CCO = 2.5V) and
HSTL_I_DCI_18 input (input V_CCO = 1.8V)
4. Combining bidirectional standards with input or
output standards. When combining bidirectional I/O
with other standards, make sure the bidirectional
standard can meet rules 1 through 3 above.
5. Additional rules for combining DCI I/O standards.
a. No more than one Single Termination type (input or
output) is allowed in the same bank.
Incompatible example:
HSTL_IV_DCI input and HSTL_III_DCI input
b. No more than one Split Termination type (input or
output) is allowed in the same bank.
12
www.xilinx.com
DS122 (v1.1) January 7, 2004
1-800-255-7778
Product Specification