XQ2V1000 Datasheet, PDF (29/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

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QPro Virtex-II 1.5V Military QML Platform FPGAs
A write operation performs a simultaneous read operation.
Three different options are available, selected by configura-
tion:
1. “WRITE_FIRST”
The “WRITE_FIRST” option is a transparent mode. The
same clock edge that writes the data input (DI) into the
memory also transfers DI into the output registers DO
as shown in Figure 32.
2. “READ_FIRST”
The “READ_FIRST” option is a read-before-write mode.
The same clock edge that writes data input (DI) into the
memory also transfers the prior content of the memory
cell addressed into the data output registers DO, as
shown in Figure 33.
3. “NO_CHANGE”
The “NO_CHANGE” option maintains the content of the
output registers, regardless of the write operation. The
clock edge during the write mode has no effect on the
content of the data output register DO. When the port is
configured as “NO_CHANGE”, only a read operation
loads a new value in the output register DO, as shown in
Figure 34.
Data_in
Internal
DI _Memory
DO
Data_out = Data_in
CLK
WE
Data_in
Address
RAM Contents
Data_out
New
aa
Old
New
New
Figure 32: WRITE_FIRST Mode
DS031_14_102000
Data_in
Internal
DI _Memory
DO
Prior stored data
CLK
WE
Data_in
Address
RAM Contents
Data_out
New
aa
Old
New
Old
Figure 33: READ_FIRST Mode
DS031_13_102000
DS122 (v1.1) January 7, 2004
www.xilinx.com
29
Product Specification
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