XQ2V1000 Datasheet, PDF (9/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

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QPro Virtex-II 1.5V Military QML Platform FPGAs
CLOCK
D1
Q1
CLK1
D2
Q2
CLK2
FDDR
DCM
180° 0°
DDR MUX
Q
D1
Q1
CLK1
D2
Q2
CLK2
FDDR
DDR MUX
Q
(50/50 duty cycle clock)
Figure 4: Double Data Rate Registers
DS031_26_100900
The DDR mechanism shown in Figure 4 can be used to mir-
ror a copy of the clock on the output. This is useful for prop-
agating a clock along the data that has an identical delay. It
is also useful for multiple clock generation, where there is a
unique clock driver for every clock load. Virtex-II devices
can produce many copies of a clock with very little skew.
Each group of two registers has a clock enable signal (ICE
for the input registers, OCE for the output registers, and
TCE for the 3-state registers). The clock enable signals are
active High by default. If left unconnected, the clock enable
for that storage element defaults to the active state.
Each IOB block has common synchronous or asynchronous
set and reset (SR and REV signals).
SR forces the storage element into the state specified by the
SRHIGH or SRLOW attribute. SRHIGH forces a logic “1”.
SRLOW forces a logic “0”. When SR is used, a second input
(REV) forces the storage element into the opposite state. The
reset condition predominates over the set condition. The ini-
tial state after configuration or global initialization state is
defined by a separate INIT0 and INIT1 attribute. By default,
the SRLOW attribute forces INIT0, and the SRHIGH attribute
forces INIT1.
For each storage element, the SRHIGH, SRLOW, INIT0,
and INIT1 attributes are independent. Synchronous or
asynchronous set/reset is consistent in an IOB block.
All the control signals have independent polarities. Any
inverter placed on a control input is automatically absorbed.
Each register or latch (independent of all other registers or
latches) (see Figure 5) can be configured as follows:
• No set or reset
• Synchronous set
• Synchronous reset
• Synchronous set and reset
• Asynchronous set (preset)
• Asynchronous reset (clear)
• Asynchronous set and reset (preset and clear)
The synchronous reset overrides a set, and an asynchro-
nous clear overrides a preset.
DS122 (v1.1) January 7, 2004
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Product Specification
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