XQ2V1000 Datasheet, PDF (2/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

QPro Virtex-II 1.5V Military QML Platform FPGAs
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Table 1: Virtex-II Field-Programmable Gate Array Family Members
CLB
(1 CLB = 4 slices = Max 128 bits)
Device
System Array
Gates Row x Col.
Slices
Maximum
Distributed
RAM Kbits
Multiplier
Blocks
XQ2V1000
1M
40 x 32 5,120
160
40
XQ2V3000
3M
64 x 56 14,336
448
96
XQ2V6000
6M
96 x 88 33,792
1,056
144
Notes:
1. See details in Table 2, "Maximum Number of User I/O Pads".
SelectRAM Blocks
18 Kbit
Blocks
40
96
144
Max RAM
(Kbits)
720
1,728
2,592
Max I/O
DCMs Pads⁽¹⁾
8
432
12
720
12
1,104
General Description
The Virtex-II family includes platform FPGAs developed for
high performance from low-density to high-density designs
that are based on IP cores and customized modules. The
family delivers complete solutions for telecommunication,
wireless, networking, video, and DSP applications, includ-
ing PCI, LVDS, and DDR interfaces.
The leading-edge 0.15 µm/0.12 µm CMOS 8-layer metal
process and the Virtex-II architecture are optimized for high
speed with low power consumption. Combining a wide vari-
ety of flexible features and a large range of densities up to
8 million system gates, the Virtex-II family enhances pro-
grammable logic design capabilities and is a powerful alter-
native to mask-programmed gates arrays. As shown in
Table 1, the QPro Virtex-II family comprises three members,
ranging from 1M to 6M system gates.
Packaging
Offerings include ball grid array (BGA) packages with
1.00 mm and 1.27 mm pitches. In addition to traditional
wire-bond interconnects, flip-chip interconnect is used in
some of the CGA offerings. The use of flip-chip interconnect
offers more I/Os than is possible in wire-bond versions of
the similar packages. Flip-chip construction offers the com-
bination of high pin count with high thermal capacity.
Table 2 shows the maximum number of user I/Os available.
The Virtex-II device/package combination table (Table 5 on
page 5) details the maximum number of I/Os for each
device and package using wire-bond or flip-chip technology.
Table 2: Maximum Number of User I/O Pads
Device
Wire-Bond
Flip-Chip
XQ2V1000
328
-
XQ2V3000
516
-
XQ2V6000
-
824
Architecture
Virtex-II Array Overview
Virtex-II devices are user-programmable gate arrays with
various configurable elements. The Virtex-II architecture is
optimized for high-density and high-performance logic
designs. As shown in Figure 1, the programmable device is
comprised of input/output blocks (IOBs) and internal config-
urable logic blocks (CLBs).
Programmable I/O blocks provide the interface between
package pins and the internal configurable logic. Most
popular and leading-edge I/O standards are supported by
the programmable IOBs.
2
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