XQ2V1000 Datasheet, PDF (28/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

QPro Virtex-II 1.5V Military QML Platform FPGAs
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Table 19 illustrates the different configurations available on
Ports A and B.
Table 19: Dual-Port Mode Configurations
Port A
16K x 1
16K x 1
Port B
16K x 1
8K x 2
Port A
8K x 2
8K x 2
Port B
8K x 2
4K x 4
Port A
4K x 4
4K x 4
Port B
4K x 4
2K x 9
Port A
2K x 9
2K x 9
Port B
2K x 9
1K x 18
Port A
1K x 18
1K x 18
Port B
1K x 18
512 x 36
Port A
512 x 36
Port B
512 x 36
16K x 1
4K x 4
8K x 2
2K x 9
4K x 4
1K x 18
2K x 9
512 x 36
16K x 1
2K x 9
8K x 2
1K x 18
4K x 4
512 x 36
16K x 1
1K x 18
8K x 2
512 x 36
16K x 1
512 x 36
If both ports are configured in either 2K x 9-bit, 1K x 18-bit,
or 512 x 36-bit configurations, the 18 Kbit block is accessi-
ble from Port A or B. If both ports are configured in either
16K x 1-bit, 8K x 2-bit, or 4K x 4-bit configurations, the
16 Kbit block is accessible from Port A or Port B. All other
configurations result in one port having access to an 18 Kbit
memory block and the other port having access to a 16 Kbit
subset of the memory block equal to 16 Kbits.
Each block SelectRAM cell is a fully synchronous memory,
as illustrated in Figure 31. The two ports have independent
inputs and outputs and are independently clocked.
18 Kbit Block SelectRAM
DIA
DIPA
ADDRA
WEA
ENA
SSRA
CLKA
DOA
DOPA
DIB
DIPB
ADDRB
WEB
ENB
SSRB
CLKB
DOB
DOPB
DS031_11_071602
Figure 31: 18 Kbit Block SelectRAM in Dual-Port Mode
Port Aspect Ratios
Table 20 shows the depth and the width aspect ratios for the
18 Kbit block SelectRAM. Virtex-II block SelectRAM also
includes dedicated routing resources to provide an efficient
interface with CLBs, block SelectRAM, and multipliers.
Table 20: 18 Kbit Block SelectRAM Port Aspect Ratio
Width Depth Address Bus Data Bus Parity Bus
1
16,384 ADDR[13:0]
DATA[0]
N/A
2
8,192 ADDR[12:0] DATA[1:0]
N/A
4
4,096 ADDR[11:0] DATA[3:0]
N/A
9
2,048 ADDR[10:0] DATA[7:0] Parity[0]
18
1,024 ADDR[9:0] DATA[15:0] Parity[1:0]
36
512
ADDR[8:0] DATA[31:0] Parity[3:0]
Read/Write Operations
The Virtex-II block SelectRAM read operation is fully syn-
chronous. An address is presented, and the read operation
is enabled by control signals WEA and WEB in addition to
ENA or ENB. Then, depending on clock polarity, a rising or
falling clock edge causes the stored data to be loaded into
output registers.
The write operation is also fully synchronous. Data and
address are presented, and the write operation is enabled
by control signals WEA or WEB in addition to ENA or ENB.
Then, again depending on the clock input mode, a rising or
falling clock edge causes the data to be loaded into the
memory cell addressed.
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DS122 (v1.1) January 7, 2004
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