XQ2V1000 Datasheet, PDF (74/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

QPro Virtex-II 1.5V Military QML Platform FPGAs
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Table 71: Pin-to-Pin Setup/Hold: Source-Synchronous Configuration
Description
Symbol
Device
Value
Data Input Set-Up and Hold Times Relative to a Forwarded Clock Input Pin,
Using DCM and Global Clock Buffer.
For situations where clock and data inputs conform to different standards,
adjust the setup and hold values accordingly using the values shown in IOB
Input Switching Characteristics Standard Adjustments, page 53.
No Delay
Global Clock and IFF with DCM
T_PSDCM/T_PHDCM
XQ2V1000
XQ2V3000
TBD
TBD
XQ2V6000
TBD
Notes:
1. IFF = Input Flip-Flop
2. The timing values were measured using the fine-phase adjustment feature of the DCM.
3. The worst-case duty-cycle distortion and DCM jitter on CLK0 and CLK180 is included in these measurements.
Units
ns
ns
ns
Source Synchronous Timing Budgets
This section describes how to use the parameters provided
in the Source-Synchronous Switching Characteristics
section to develop system-specific timing budgets. The fol-
lowing analysis provides information necessary for deter-
mining QPro Virtex-II contributions to an overall system
timing analysis. No assumptions are made about the effects
of Inter-Symbol Interference or PCB skew.
QPro Virtex-II Transmitter Data-Valid Window (T_X)
T_X is the minimum aggregate valid data period for a
source-synchronous data bus at the pins of the device and
is calculated as follows:
T_X = Data Period - [Jitter⁽¹⁾ + Duty Cycle Distortion⁽²⁾ +
TCKSKEW⁽³⁾ + TPKGSKEW⁽⁴⁾]
Notes:
1. Jitter values and accumulation methodology to be provided in
a future release of this document. The absolute period jitter
values found in the DCM Timing Parameters section of the
particular DCM output clock used to clock the IOB FF can be
used for a best-case analysis.
2. This value depends on the clocking methodology used. See
Note 1 for Table 68.
3. This value represents the worst-case clock-tree skew
observable between sequential I/O elements. Significantly
less clock-tree skew exists for I/O registers that are close to
each other and fed by the same or adjacent clock-tree
branches. Use the Xilinx FPGA_Editor and Timing Analyzer
tools to evaluate clock skew specific to your application.
4. These values represent the worst-case skew between any
two balls of the package: shortest flight time to longest flight
time from Pad to Ball.
QPro Virtex-II Receiver Data-Valid Window (R_X)
R_X is the required minimum aggregate valid data period for
a source-synchronous data bus at the pins of the device
and is calculated as follows:
R_X = [TSAMP⁽¹⁾ + TCKSKEW⁽²⁾ + TPKGSKEW⁽³⁾]
Notes:
1. This parameter indicates the total sampling error of QPro
Virtex-II DDR input registers across voltage, temperature,
and process. The characterization methodology uses the
DCM to capture the DDR input registers’ edges of operation.
These measurements include:
- CLK0 and CLK180 DCM jitter in a quiet system
- Worst-case duty-cycle distortion
- DCM accuracy (phase offset)
- DCM phase shift resolution
These measurements do not include package or clock tree
skew.
2. This value represents the worst-case clock-tree skew
observable between sequential I/O elements. Significantly
less clock-tree skew exists for I/O registers that are close to
each other and fed by the same or adjacent clock-tree
branches. Use the Xilinx FPGA_Editor and Timing Analyzer
tools to evaluate clock skew specific to your application.
3. These values represent the worst-case skew between any
two balls of the package: shortest flight time to longest flight
time from Pad to Ball.
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