XQ2V1000 Datasheet, PDF (62/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

QPro Virtex-II 1.5V Military QML Platform FPGAs
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Clock Distribution Switching Characteristics
Table 48: Clock Distribution Switching Characteristics
Description
Global Clock Buffer I input to O output
Symbol
T_GIO
Value
0.59
Units
ns
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used (see Figure 49). The values listed below are
worst-case. Precise values are provided by the timing analyzer.
Table 49: CLB Switching Characteristics
Description
Symbol
Min
Max
Units
Combinatorial Delays
4-input function: F/G inputs to X/Y outputs
T_ILO
-
0.44
ns
5-input function: F/G inputs to F5 output
T_IF5
-
0.72
ns
5-input function: F/G inputs to X output
T_IF5X
-
0.95
ns
FXINA or FXINB inputs to Y output via MUXFX
T_IFXY
-
0.45
ns
FXINA input to FX output via MUXFX
T_INAFX
-
0.32
ns
FXINB input to FX output via MUXFX
T_INBFX
-
0.32
ns
SOPIN input to SOPOUT output via ORCY
T_SOPSOP
-
0.44
ns
Incremental delay routing through transparent latch to XQ/YQ
outputs
T_IFNCTL
-
0.51
ns
Sequential Delays
FF Clock CLK to XQ/YQ outputs
Latch Clock CLK to XQ/YQ outputs
Setup and Hold Times Before/After Clock CLK
T_CKO
T_CKLO
-
0.57
ns
-
0.68
ns
BX/BY inputs
DY inputs
DX inputs
CE input
SR/BY inputs (synchronous)
Clock CLK
T_DICK/T_CKDI
0.37/–0.09
-
ns
T_DYCK/T_CKDY 0.37/–0.09
-
ns
T_DXQK/T_CKDX 0.37/–0.09
-
ns
T_CECK/T_CKCE 0.24/–0.08
-
ns
T_SRCK/T_SCKR 0.26/–0.03
-
ns
Minimum Pulse Width, High
Minimum Pulse Width, Low
Set/Reset
T_CH
0.77
-
ns
T_CL
0.77
-
ns
Minimum Pulse Width, SR/BY inputs
Delay from SR/BY inputs to XQ/YQ outputs (asynchronous)
Toggle Frequency (MHz) (for export control)
T_RPW
T_RQ
F_TOG
0.77
-
ns
-
1.34
ns
-
650
MHz
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DS122 (v1.1) January 7, 2004
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