XQ2V1000 Datasheet, PDF (3/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

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QPro Virtex-II 1.5V Military QML Platform FPGAs
Global Clock Mux
DCM
DCM
IOB
Configurable Logic
Programmable I/Os
CLB Block SelectRAM
Multiplier
DS031_28_100900
Figure 1: Virtex-II Architecture Overview
The internal configurable logic includes four major elements
organized in a regular array:
• Configurable Logic Blocks (CLBs) provide functional
elements for combinatorial and synchronous logic,
including basic storage elements. BUFTs (3-state
buffers) associated with each CLB element drive
dedicated segmentable horizontal routing resources.
• Block SelectRAM memory modules provide large
18 Kbit storage elements of dual-port RAM.
• Multiplier blocks are 18-bit x 18-bit dedicated
multipliers.
• DCM (Digital Clock Manager) blocks provide
self-calibrating, fully digital solutions for clock
distribution delay compensation, clock multiplication
and division, coarse- and fine-grained clock phase
shifting.
A new generation of programmable routing resources called
Active Interconnect Technology interconnects all of these
elements. The general routing matrix (GRM) is an array of
routing switches. Each programmable element is tied to a
switch matrix, allowing multiple connections to the general
routing matrix. The overall programmable interconnection is
hierarchical and designed to support high-speed designs.
All programmable elements, including the routing
resources, are controlled by values stored in static memory
cells. These values are loaded in the memory cells during
configuration and can be reloaded to change the functions
of the programmable elements.
Virtex-II Features
This section briefly describes Virtex-II features.
Input/Output Blocks (IOBs)
IOBs are programmable and can be categorized as follows:
• Input block with an optional single-data-rate or
double-data-rate (DDR) register
• Output block with an optional single-data-rate or DDR
register, and an optional 3-state buffer, to be driven
directly or through a single or DDR register
• Bidirectional block (any combination of input and output
configurations)
These registers are either edge-triggered D-type flip-flops
or level-sensitive latches.
IOBs support the following single-ended I/O standards:
• LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)
• PCI compatible (33 MHz) at 3.3V
• CardBus compliant (33 MHz) at 3.3V
• GTL and GTLP
• HSTL (Class I, II, III, and IV)
• SSTL (3.3V and 2.5V, Class I and II)
• AGP-2X
The digitally controlled impedance (DCI) I/O feature auto-
matically provides on-chip termination for each I/O element.
The IOB elements also support the following differential sig-
naling I/O standards:
• LVDS
• BLVDS (Bus LVDS)
• ULVDS
• LDT
• LVPECL
Two adjacent pads are used for each differential pair. Two or
four IOB blocks connect to one switch matrix to access the
routing resources.
DS122 (v1.1) January 7, 2004
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Product Specification
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