XQ2V1000 Datasheet, PDF (48/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

QPro Virtex-II 1.5V Military QML Platform FPGAs
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Table 34: Quiescent Supply Current
Symbol
Description
Device
Min
Typical
Max Units
I_CCINTQ
Quiescent V_CCINT supply current
XQ2V1000
XQ2V3000
-
XQ2V6000
100
0.50
200
1.30
A
250
1.50
Quiescent V_CCO supply current^(1,2)
XQ2V1000
I_CCOQ
XQ2V3000
-
XQ2V6000
Quiescent V_CCAUX supply current^(1,2)
XQ2V1000
I_CCAUXQ
XQ2V3000
-
XQ2V6000
1.0
6.25
2.0
6.25
mA
2.0
6.25
10
30
20
95
mA
25
95
Notes:
1. With no output current loads and no active input pull-up resistors. All I/O pins are 3-stated and floating.
2. If DCI or differential signaling is used, more accurate values can be obtained by using the Power Estimator or XPOWER.
3. Data are retained even if V_CCO drops to 0 V.
4. Values specified for quiescent supply current parameters are Military Grade.
Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current
during power-on to ensure proper device operation. The
actual current consumed depends on the power-on ramp
rate of the power supply.
The V_CCINT, V_CCAUX, and V_CCO power supplies shall each
ramp on no faster than 200 µs and no slower than 50 ms.
Ramp on is defined as: 0 V_DC to minimum supply voltages.
Table 35 shows the minimum current required by QPro
Virtex-II devices for proper power on and configuration.
Power supplies can be turned on in any sequence.
If any V_CCO bank powers up before V_CCAUX, then each bank
draws up to 300 mA, worst case, until the V_CCAUX powers
on¹. This does not harm the device. If the current is limited
to the minimum value above, or larger, the device powers on
properly after all three supplies have passed through their
power on reset threshold voltages.
Once initialized and configured, use the power calculator to
estimate current drain on these supplies.
Table 35: Maximum Power On Current Required for
QPro Virtex-II Devices
Device (mA)
Current
XQ2V1000 XQ2V3000 XQ2V6000
I_CCINTMAX
500
1300
1500
I_CCAUXMAX
30
95
95
I_CCOMAX
6.25
6.25
6.25
Notes:
1. Values specified for power on current parameters are Military
Grade.
2. I_CCOMAX values listed here apply to the entire device (all
banks).
General Power Supply Requirements
Proper decoupling of all FPGA power supplies is essential.
Consult Xilinx Application Note XAPP623 for detailed infor-
mation on power distribution system design.
V_CCAUX powers critical resources in the FPGA. Thus,
V_CCAUX is especially susceptible to power supply noise.
Changes in V_CCAUX voltage outside of 200 mV peak to peak
should take place at a rate no faster than 10 mV per milli-
second. Techniques to help reduce jitter and period distor-
tion are provided in Xilinx Answer Record 13756, available
at www.support.xilinx.com.
V_CCAUX can share a power plane with 3.3V V_CCO, but only if
V_CCO does not have excessive noise. Using simultaneously
switching output (SSO) limits are essential for keeping
power supply noise to a minimum. Refer to XAPP689,
“Managing Ground Bounce in Large FPGAs,” to determine
the number of simultaneously switching outputs allowed per
bank at the package level.
1. The 300 mA is transient current (peak). It eventually disappears even if VCCAUX does not power up.
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