DS162 Datasheet, PDF (70/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 76: Package Skew (Cont’d)
Symbol
T_PKGSKEW
Description
Package Skew⁽¹⁾
Device
XC6SLX150
XC6SLX150T
Package⁽³⁾
CSG484
FG(G)484
FG(G)676
FG(G)900
CSG484
FG(G)484
FG(G)676
FG(G)900
Value
84
103
115
121
83
88
141
120
Units
ps
ps
ps
ps
ps
ps
ps
ps
Notes:
1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from Pad to Ball.
2. Package delay information is available for these device/package combinations. This information can be used to deskew the package.
3. Some of these devices are available in both Pb and Pb-free (additional G) packages as standard ordering options.
Table 77: Sample Window
Symbol
T_SAMP
T_{SAMP_BUFIO2}
Description
Sampling Error at Receiver Pins⁽²⁾
Sampling Error at Receiver Pins using
BUFIO2⁽³⁾
Device⁽¹⁾
-4
Speed Grade
-3
-2
Units
-1L
All
510
510
560
ps
All
430
430
480
ps
Notes:
1. LX devices are not available with a -4 speed grade; LXT devices are not available with a -1L speed grade.
2. This parameter indicates the total sampling error of Spartan-6 FPGA DDR input registers, measured across voltage, temperature, and process. The
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 DCM jitter
- DCM accuracy (phase offset)
- DCM phase shift resolution
These measurements do not include package or clock tree skew.
3. This parameter indicates the total sampling error of Spartan-6 FPGA DDR input registers, measured across voltage, temperature, and process. The
characterization methodology uses the BUFIO2 clock network and IODELAY to capture the DDR input registers’ edges of operation. These
measurements do not include package or clock tree skew.
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
70