DS162 Datasheet, PDF (55/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 57: Switching Characteristics for the Phase-Shift Clock in Variable Phase Mode⁽¹⁾
Symbol
Description
Amount of Phase Shift
Units
Phase Shifting Range
MAX_STEPS⁽²⁾
When CLKIN < 60 MHz, the maximum allowed
number of DCM_DELAY_STEP steps for a
given CLKIN clock period, where T = CLKIN
clock period in ns. When using
CLKIN_DIVIDE_BY_2 = TRUE, double the
clock-effective clock period.
±(INTEGER(10 x (TCLKIN – 3 ns)))
When CLKIN ≥ 60 MHz, the maximum allowed
number of DCM_DELAY_STEP steps for a
given CLKIN clock period, where T = CLKIN
clock period in ns. When using
CLKIN_DIVIDE_BY_2 = TRUE, double the
clock-effective clock period.
±(INTEGER(15 x (TCLKIN – 3 ns)))
steps
steps
FINE_SHIFT_RANGE_MIN
Minimum guaranteed delay for variable phase
shifting.
±(MAX_STEPS x DCM_DELAY_STEP_MIN)
ns
FINE_SHIFT_RANGE_MAX
Maximum guaranteed delay for variable phase
shifting
±(MAX_STEPS x DCM_DELAY_STEP_MAX)
ns
Notes:
1. The values in this table are based on the operating conditions described in Table 51 and Table 56.
2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM has no initial fixed-phase shifting, that is, the PHASE_SHIFT
attribute is set to 0.
3. The DCM_DELAY_STEP values are provided at the end of Table 52.
Table 58: Miscellaneous DCM Timing Parameters⁽¹⁾
Symbol
Description
DCM_RST_PW_MIN
Minimum duration of a RST pulse width
Min Max
Units
3
– CLKIN cycles
Notes:
1. This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV). The DCM
DFS outputs (CLKFX, CLKFXDV, CLKFX180) are unaffected.
Table 59: Frequency Synthesis
Attribute
CLKFX_MULTIPLY (DCM_SP)
CLKFX_DIVIDE (DCM_SP)
CLKDV_DIVIDE (DCM_SP)
CLKFX_MULTIPLY (DCM_CLKGEN)
CLKFX_DIVIDE (DCM_CLKGEN)
CLKFXDV_DIVIDE (DCM_CLKGEN)
Min
Max
2
32
1
32
1.5
16
2
256
1
256
2
32
Table 60: DCM Switching Characteristics
Symbol
Description
T_{DMCCK_PSEN}/ T_{DMCKC_PSEN}
PSEN Setup/Hold
T_{DMCCK_PSINCDEC}/ T_{DMCKC_PSINCDEC}
PSINCDEC Setup/Hold
T_{DMCKO_PSDONE}
Clock to out of PSDONE
Speed Grade
Units
-4
-3
-2
-1L
1.50 1.50 1.50 1.50 ns
0.00 0.00 0.00 0.00
1.50 1.50 1.50 1.50 ns
0.00 0.00 0.00 0.00
1.50 1.50 1.50 1.50 ns
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
55