DS162 Datasheet, PDF (41/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Block RAM Switching Characteristics
Table 42: Block RAM Switching Characteristics
Symbol
Description
Speed Grade
Units
-4
-3
-2
-1L
Block RAM Clock to Out Delays
T_{RCKO_DO}
T_{RCKO_DO_REG}
Clock CLK to DOUT output (without output register)⁽¹⁾
Clock CLK to DOUT output (with output register)⁽²⁾
Setup and Hold Times Before/After Clock CLK
T_{RCCK_ADDR}/T_{RCKC_ADDR}
ADDR inputs⁽³⁾
T_{RDCK_DI}/T_{RCKD_DI}
DIN inputs ⁽⁴⁾
1.85
1.60
0.35
0.10
0.30
0.10
2.10
1.75
0.40
0.12
0.30
0.10
2.90
1.90
0.40
0.15
0.30
0.12
3.50 ns, Max
2.30 ns, Max
0.50 ns, Min
0.15
0.40 ns, Min
0.15
T_{RCCK_EN}/T_{RCKC_EN}
Block RAM Enable (EN) input
0.21 0.22 0.28 0.26 ns, Min
0.05 0.06 0.10 0.10
T_{RCCK_REGCE}/T_{RCKC_REGCE}
CE input of output register
0.20 0.20 0.25 0.28 ns, Min
0.10 0.10 0.12 0.15
T_{RCCK_WE}/T_{RCKC_WE}
Write Enable (WE) input
0.25 0.33 0.46 0.28 ns, Min
0.10 0.10 0.12 0.15
Maximum Frequency
F_MAX
Block RAM in all modes
320 280 260 150 MHz
Notes:
1. T_{RCKO_DO} includes T_{RCKO_DOA} and T_{RCKO_DOPA} as well as the B port equivalent timing parameters.
2. T_{RCKO_DO_REG} includes T_{RCKO_DOA_REG} and T_{RCKO_DOPA_REG} as well as the B port equivalent timing parameters.
3. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible.
4. T_{RDCK_DI} includes both A and B inputs as well as the parity inputs of A and B.
DS162 (v1.9) August 23, 2010
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Advance Product Specification
41