DS162 Datasheet, PDF (40/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
CLB Distributed RAM Switching Characteristics (SLICEM Only)
Table 40: CLB Distributed RAM Switching Characteristics (SLICEM Only)
Symbol
Description
Sequential Delays
T_SHCKO
Clock to A – D outputs
Clock to A – D outputs (direct output path)
Setup and Hold Times Before/After Clock CLK
T_DS/T_DH
AX – DX or AI – DI inputs to CLK
T_AS/T_AH
Address An inputs to clock
T_WS/T_WH
WE input to clock
T_CECK/T_CKCE
CE input to CLK
-4
1.26
0.96
0.59
0.17
0.28
0.35
0.31
–0.08
0.31
–0.08
Speed Grade
-3
-2
1.55 2.12
1.20 1.60
0.73
0.22
0.32
0.42
0.37
–0.08
0.37
–0.08
1.04
0.37
0.40
0.67
0.59
–0.08
0.59
–0.08
Units
-1L
2.56 ns, Max
ns, Max
1.17
0.33
0.26
0.71
0.59
–0.27
0.59
–0.27
ns, Min
ns, Min
ns, Min
ns, Min
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 41: CLB Shift Register Switching Characteristics
Symbol
Description
Sequential Delays
T_REG
Clock to A – D outputs
Clock to A – D outputs (direct output path)
Setup and Hold Times Before/After Clock CLK
T_WS/T_WH
WE input to CLK
T_CECK/T_CKCE
CE input to CLK
T_DS/T_DH
AX – DX or AI – DI inputs to CLK
Speed Grade
Units
-4
-3
-2
-1L
1.35 1.78 2.14 2.89 ns, Max
1.24 1.65 1.95
ns, Max
0.20
–0.07
0.27
0.36
0.07
0.11
0.24
–0.07
0.29
0.38
0.09
0.14
0.36
–0.07
0.52
0.40
0.18
0.28
0.59
–0.17
0.59
–0.17
1.16
0.28
ns, Min
ns, Min
ns, Min
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
40