DS162 Datasheet, PDF (50/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 52: Switching Characteristics for the Delay-Locked Loop (DLL)⁽¹⁾
Speed Grade
Symbol
Description
-4
-3
-2
-1L
Units
Min Max Min Max Min Max Min Max
Output Frequency Ranges
CLKOUT_FREQ_CLK0
Frequency for the CLK0 and
CLK180 outputs.
5 280 5 280 5 250
MHz
CLKOUT_FREQ_CLK90
Frequency for the CLK90 and
CLK270 outputs.
5 200 5 200 5 200
MHz
CLKOUT_FREQ_2X
Frequency for the CLK2X and
CLK2X180 outputs.
10 375 10 375 10 334
MHz
CLKOUT_FREQ_DV
Output Clock Jitter^(2)(3)(4)
Frequency for the CLKDV output.
0.3125 186 0.3125 186 0.3125 166
MHz
CLKOUT_PER_JITT_0
Period jitter at the CLK0 output.
– ±100 – ±100 – ±100 –
ps
CLKOUT_PER_JITT_90
Period jitter at the CLK90 output.
– ±150 – ±150 – ±150 –
ps
CLKOUT_PER_JITT_180
Period jitter at the CLK180 output.
– ±150 – ±150 – ±150 –
ps
CLKOUT_PER_JITT_270
Period jitter at the CLK270 output.
– ±150 – ±150 – ±150 –
ps
CLKOUT_PER_JITT_2X
Period jitter at the CLK2X and
CLK2X180 outputs.
Maximum = ±[0.5% of CLKIN period + 100]
ps
CLKOUT_PER_JITT_DV1
Period jitter at the CLKDV output
when performing integer division.
– ±150 – ±150 – ±150
ps
CLKOUT_PER_JITT_DV2
Period jitter at the CLKDV output
when performing non-integer
division.
Maximum = ±[0.5% of CLKIN
period + 100]
ps
Duty Cycle⁽⁴⁾
CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0,
CLK90, CLK180, CLK270, CLK2X,
CLK2X180, and CLKDV outputs,
Typical = ±[1% of CLKIN period + 350]
ps
including the BUFGMUX and clock
tree duty-cycle distortion.
Phase Alignment⁽⁴⁾
CLKIN_CLKFB_PHASE
Phase offset between the CLKIN
and CLKFB inputs
(CLK_FEEDBACK = 1X).
Phase offset between the CLKIN
and CLKFB inputs
(CLK_FEEDBACK = 2X).
– ±150 – ±150 – ±150 – ±250
ps
Max
– ±250 – ±250 – ±250
CLKOUT_PHASE_DLL
Phase offset between DLL outputs
for CLK0 to CLK2X (not CLK2X180).
Maximum = ±[1% of CLKIN period + 100]
ps
Phase offset between DLL outputs
for all others.
Maximum = ±[1% of CLKIN period + 150]
ps
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
50