DS162 Datasheet, PDF (53/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 55: Switching Characteristics for the Digital Frequency Synthesizer DFS (DCM_CLKGEN)⁽¹⁾
Speed Grade
Symbol
Description
-4
-3
-2
-1L
Units
Min Max Min Max Min Max Min Max
Output Frequency Ranges (DCM_CLKGEN)
CLKOUT_FREQ_FX
Frequency for the CLKFX and
CLKFX180 outputs
5 375 5 375 5 333 5 200 MHz
CLKOUT_FREQ_FXDV
Output Clock Jitter⁽²⁾⁽³⁾
Frequency for the CLKFXDV
output
0.15625 187.5 0.15625 187.5 0.15625 166.5 0.15625 100 MHz
CLKOUT_PER_JITT_FX Period jitter at the CLKFX and
CLKFX180 outputs.
Typical = ±[0.2% of CLKFX period + 100]
ps
CLKOUT_PER_JITT_FXDV Period jitter at the CLKFXDV
output.
Typical = ±[0.2% of CLKFX period + 100]
ps
CLKFX_FREEZE_VAR
CLKFX period change in free
running oscillator mode at the
same temperature.
FCLKFX > 50 MHz
CLKFX period change in free
running oscillator mode at the
same temperature.
FCLKFX < 50 MHz
Maximum = ±3% of CLKFX period
ps
Maximum = ±5% of CLKFX period
ps
CLKFX_FREEZE_TEMP
_SLOPE
Duty Cycle⁽⁴⁾⁽⁵⁾
CLKFX period will change in
free_oscillator mode over
temperature. Add to
CLKFX_FREEZE_VAR to
determine total CLKFX period
change. Percentage change for
CLKFX period over 1°C.
Maximum = 0.1
%/°C
CLKOUT_DUTY_CYCLE_ Duty cycle precision for the
FX
CLKFX and CLKFX180 outputs,
including the BUFGMUX and
Maximum = ±[1% of CLKFX period + 350]
ps
clock tree duty-cycle distortion
CLKOUT_DUTY_CYCLE_ Duty cycle precision for the
FXDV
CLKFXDV outputs, including the
BUFGMUX and clock tree
Maximum = ±[1% of CLKFX period + 350]
ps
duty-cycle distortion
Lock Time
LOCK_FX⁽²⁾
The time from deassertion at the
DCM’s Reset input to the rising
transition at its LOCKED output.
The DFS asserts LOCKED when
the CLKFX, CLKFX180, and
CLKFXDV signals are valid.
–
50
–
50
–
50
–
50 ms
Lock time requires
CLKFX_DIVIDE < F_IN/(0.50
MHz)
when:
5 MHz < F_CLKIN < 50 MHz
when:
F_CLKIN > 50 MHz
–
5
–
5
–
5
–
5 ms
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
53