DS162 Datasheet, PDF (59/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 65: Global Clock Input to Output Delay With PLL in Source-Synchronous Mode
Symbol
Description
Device
Speed Grade
Units
-4
-3
-2
-1L
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in Source-Synchronous Mode.
T_{ICKOFPLL_0}
Global Clock and OUTFF with PLL
XC6SLX4
N/A
5.81
6.87
ns
XC6SLX9
N/A
5.80
6.86
ns
XC6SLX16
N/A
5.77
6.79
ns
XC6SLX25
N/A
5.35
6.10
ns
XC6SLX25T
5.00
5.35
6.10
N/A
ns
XC6SLX45
N/A
6.03
7.02
ns
XC6SLX45T
5.59
6.03
7.02
N/A
ns
XC6SLX75
N/A
5.41
6.22
ns
XC6SLX75T
4.96
5.41
6.22
N/A
ns
XC6SLX100
N/A
5.42
6.21
ns
XC6SLX100T
5.01
5.42
6.21
N/A
ns
XC6SLX150
N/A
5.06
5.86
ns
XC6SLX150T
4.59
5.06
5.86
N/A
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible
IOB and CLB flip-flops are clocked by the global clock net.
2. PLL output jitter is included in the timing calculation.
Table 66: Global Clock Input to Output Delay With DCM and PLL in System-Synchronous Mode
Symbol
Description
Device
Speed Grade
Units
-4
-3
-2
-1L
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in System-Synchronous Mode
and PLL in DCM2PLL Mode.
T_{ICKOFDCM_PLL}
Global Clock and OUTFF with DCM and XC6SLX4
N/A
5.01
5.90
ns
PLL
XC6SLX9
N/A
5.01
5.89
ns
XC6SLX16
N/A
5.12
5.94
ns
XC6SLX25
N/A
5.09
5.92
ns
XC6SLX25T
4.70
5.09
5.92
N/A
ns
XC6SLX45
N/A
4.98
5.83
ns
XC6SLX45T
4.63
4.98
5.83
N/A
ns
XC6SLX75
N/A
5.04
5.88
ns
XC6SLX75T
4.68
5.04
5.88
N/A
ns
XC6SLX100
N/A
5.07
5.92
ns
XC6SLX100T
4.76
5.07
5.92
N/A
ns
XC6SLX150
N/A
4.73
5.31
ns
XC6SLX150T
4.44
4.73
5.31
N/A
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible
IOB and CLB flip-flops are clocked by the global clock net.
2. DCM and PLL output jitter are already included in the timing calculation.
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
59