DS162 Datasheet, PDF (18/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Production Silicon and ISE Software Status
In some cases, a particular family member (and speed grade) is released to production before a speed specification is
released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent
speed specification releases. Table 27 lists the production released Spartan-6 family member, speed grade, and the
minimum corresponding supported speed specification version and ISE® software revisions. The ISE software and speed
specifications listed are the minimum releases required for production. All subsequent releases of software and speed
specifications are valid.
Table 27: Spartan-6 Device Production Software and Speed Specification Release⁽¹⁾
Device
Speed Grade Designations⁽²⁾
-4
-3
-3N
-2
-1L
XC6SLX4
N/A
N/A
XC6SLX9
N/A
XC6SLX16
XC6SLX25
N/A
ISE 12.1 v1.08 ISE 12.2 v1.11⁽³⁾ ISE 11.5 v1.06
N/A
ISE 12.2 v1.11⁽³⁾
XC6SLX25T
ISE 12.2 v1.11⁽³⁾
N/A
XC6SLX45
XC6SLX45T
N/A
ISE 12.1 v1.08 ISE 12.2 v1.11⁽³⁾ ISE 11.5 v1.07
ISE 12.2 v1.11⁽³⁾ ISE 12.1 v1.08 ISE 12.2 v1.11⁽³⁾ ISE 12.1 v1.08
N/A
XC6SLX75
N/A
ISE 12.2 v1.11⁽³⁾
XC6SLX75T
ISE 12.2 v1.11⁽³⁾
N/A
XC6SLX100
N/A
ISE 12.2 v1.11⁽³⁾
XC6SLX100T
XC6SLX150
ISE 12.2 v1.11⁽³⁾
N/A
N/A
ISE 12.2 v1.11⁽³⁾
XC6SLX150T
ISE 12.2 v1.11⁽³⁾
N/A
Notes:
1. Blank entries indicate a device and/or speed grade in advance or preliminary status.
2. As marked with an N/A, LX devices are not available with a -4 speed grade; LXT devices are not available with a -1L speed grade; LX4 devices are
not available with a -3N speed grade.
3. ISE 12.2 software with v1.11 speed specification is available using ISE 12.2 software and the 12.2 Speed Files Patch available on the Xilinx
Download Center.
IOB Pad Input/Output/3-State Switching Characteristics
Table 28 summarizes the values of standard-specific data
input delay adjustments, output delays terminating at pads
(based on standard) and 3-state delays.
T_IOPI is described as the delay from IOB pad through the
input buffer to the I-pin of an IOB pad. The delay varies
depending on the capability of the SelectIO input buffer.
T_IOOP is described as the delay from the O pin to the IOB
pad through the output buffer of an IOB pad. The delay
varies depending on the capability of the SelectIO output
buffer.
T_IOTP is described as the delay from the T pin to the IOB
pad through the output buffer of an IOB pad, when 3-state is
disabled. The delay varies depending on the SelectIO
capability of the output buffer.
Table 29 summarizes the value of T_IOTPHZ. T_IOTPHZ is
described as the delay from the T pin to the IOB pad
through the output buffer of an IOB pad, when 3-state is
enabled (i.e., a high impedance state).
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
18