DS162 Datasheet, PDF (52/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 54: Switching Characteristics for the Digital Frequency Synthesizer (DFS) for DCM_SP⁽¹⁾
Speed Grade
Symbol
Description
-4
-3
-2
-1L
Units
Min Max Min Max Min Max Min Max
Output Frequency Ranges
CLKOUT_FREQ_FX
Output Clock Jitter⁽²⁾⁽³⁾
Frequency for the CLKFX and
CLKFX180 outputs
5 375 5 375 5 333
MHz
CLKOUT_PER_JITT_FX
Duty Cycle⁽⁴⁾⁽⁵⁾
Period jitter at the CLKFX and
CLKFX180 outputs. When
CLKIN < 20 MHz
Period jitter at the CLKFX and
CLKFX180 outputs. When
CLKIN > 20 MHz
Use the Clocking Wizard
ps
Typical = ±(1% of CLKFX period + 100)
ps
Duty cycle precision for the CLKFX
CLKOUT_DUTY_CYCLE_FX
and CLKFX180 outputs including the
BUFGMUX and clock tree duty-cycle
Maximum = ±(1% of CLKFX period + 350)
ps
distortion
Phase Alignment⁽⁵⁾
CLKOUT_PHASE_FX
Phase offset between the DFS
CLKFX output and the DLL CLK0
output when both the DFS and DLL
are used
– ±200 – ±200 – ±200 – ±250 ps
Phase offset between the DFS
CLKOUT_PHASE_FX180
CLKFX180 output and the DLL CLK0
output when both the DFS and DLL
Maximum = ±(1% of CLKFX period + 200)
ps
are used
LOCKED Time
LOCK_FX⁽²⁾
When 5 MHz < FCLKIN < 50 MHz,
the time from deassertion at the
DCM’s reset input to the rising
transition at its LOCKED output. The
DFS asserts LOCKED when the
–
5
–
5
–
5
–
5 ms
CLKFX and CLKFX180 signals are
valid. When using both the DLL and
the DFS, use the longer locking time.
When FCLKIN > 50 MHz, the time
from deassertion at the DCM’s reset
input to the rising transition at its
LOCKED output. The DFS asserts
LOCKED when the CLKFX and
– 0.45 – 0.45 – 0.45 – 0.60 ms
CLKFX180 signals are valid. When
using both the DLL and the DFS, use
the longer locking time.
Notes:
1. The values in this table are based on the operating conditions described in Table 2 and Table 53.
2. For optimal jitter tolerance and a faster LOCK time, use the CLKIN_PERIOD attribute.
3. Output jitter is characterized with no input jitter. Output jitter strongly depends on the environment, including the number of SSOs, the output drive
strength, CLB utilization, CLB switching activities, switching frequency, power supply, and PCB design. The actual maximum output jitter depends on
the system application.
4. The CLKFX, CLKFXDV, and CLKFX180 outputs have a duty cycle of approximately 50%.
5. Some duty cycle and alignment specifications include a percentage of the CLKFX output period. For example, this data sheet specifies a maximum
CLKFX jitter of ±(1% of CLKFX period + 200 ps). Assuming that the CLKFX output frequency is 100 MHz, the equivalent CLKFX period is 10 ns, and
1% of 10 ns is 0.1 ns or 100 ps. Accordingly, the maximum jitter is ±(100 ps + 200 ps) = ±300 ps.
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
52