DS162 Datasheet, PDF (36/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Input/Output Logic Switching Characteristics
Table 34: ILOGIC2 Switching Characteristics
Symbol
Description
Setup/Hold
T_ICE0CK/T_ICKCE0
CE0 pin Setup/Hold with respect to CLK
T_ISRCK/T_ICKSR
SR pin Setup/Hold with respect to CLK
T_IDOCK/T_IOCKD
T_IDOCKD/T_IOCKDD
D pin Setup/Hold with respect to CLK without Delay
DDLY pin Setup/Hold with respect to CLK (using IODELAY2)
Combinatorial
T_IDI
T_IDID
Sequential Delays
T_IDLO
T_IDLOD
T_ICKQ
T_{RQ_ILOGIC2}
D pin to O pin propagation delay, no Delay
DDLY pin to O pin propagation delay (using IODELAY2)
D pin to Q pin using flip-flop as a latch without Delay
DDLY pin to Q1 pin using flip-flop as a latch (using IODELAY2)
CLK to Q outputs
SR pin to Q outputs
Table 35: OLOGIC2 Switching Characteristics
Symbol
Description
Setup/Hold
T_ODCK/T_OCKD
T_OOCECK/T_OCKOCE
T_OSRCK/T_OCKSR
D1/D2 pins Setup/Hold with respect to CLK
OCE pin Setup/Hold with respect to CLK
SR pin Setup/Hold with respect to CLK
T_OTCK/T_OCKT
T1/T2 pins Setup/Hold with respect to CLK
T_OTCECK/T_OCKTCE
TCE pin Setup/Hold with respect to CLK
Sequential Delays
T_OCKQ
T_{RQ_OLOGIC2}
CLK to OQ/TQ out
SR pin to OQ/TQ out
Speed Grade
Units
-4
-3
-2
-1L
0.56 0.56 0.79 1.24 ns
–0.30 –0.25 –0.22 –0.55
0.74 0.74 0.98 1.35 ns
–0.23 –0.22 –0.20 –0.49
1.19 1.36 1.73 1.97 ns
–0.83 –0.83 –0.83 –1.09
0.31 0.47 0.54 0.64 ns
0.00 0.00 0.00 –0.16
0.95 1.28 1.53 1.97 ns
0.23 0.39 0.44 0.64 ns
1.56 1.86 2.39 3.22 ns
0.68 0.97 1.20 1.89 ns
1.03 1.24 1.43 1.66 ns
1.81 1.81 2.50 3.05 ns
Speed Grade
Units
-4
-3
-2
-1L
0.60 0.86 1.18 1.15 ns
–0.05 –0.05 0.00 –0.26
0.75 0.75 1.01 0.56 ns
–0.10 –0.10 –0.05 –0.22
0.68 0.79 1.03 1.09 ns
–0.28 –0.28 –0.23 –0.46
0.24 0.56 0.83 0.86 ns
–0.08 –0.06 –0.01 –0.18
0.58 0.72 1.18 0.47 ns
–0.06 –0.06 –0.01 –0.12
0.55 0.51 0.74 0.97 ns
1.81 1.81 2.50 3.05 ns
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
36