DS162 Datasheet, PDF (16/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Endpoint Block for PCI Express Designs Switching Characteristics
The Endpoint block for PCI Express is available in the Spartan-6 LXT family. Consult the Spartan-6 FPGA Integrated
Endpoint Block for PCI Express for further information.
Table 24: Maximum Performance for PCI Express Designs
Symbol
Description
F_PCIEUSER
User clock maximum frequency
Speed Grade
Units
-4
-3
-2
-1L
62.5
62.5
62.5
N/A
MHz
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in
Spartan-6 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values
are subject to the same guidelines as the Switching Characteristics, page 17.
Table 25: Interface Performances
Description
Networking Applications⁽¹⁾
Speed Grade
Units
-4
-3
-2
-1L
SDR LVDS transmitter or receiver (using IOB SDR register)
400
400
375
Mb/s
DDR LVDS transmitter or receiver (using IOB ODDR2/IDDR2 register)
800
800
750
Mb/s
SDR LVDS transmitter (using OSERDES2; DATA WIDTH = 2 to 8)
1080
1050
950
Mb/s
DDR LVDS transmitter (using OSERDES2; DATA WIDTH = 2 to 8)
1080
1050
950
Mb/s
SDR LVDS receiver (using ISERDES2; DATA WIDTH = 2 to 8)
1080
1050
950
Mb/s
DDR LVDS receiver (using ISERDES2; DATA WIDTH = 2 to 8)
1080
1050
950
Memory Interfaces (Implemented using the Spartan-6 FPGA Memory Controller Block)⁽²⁾
Mb/s
Standard Performance (standard V_CCINT)
DDR
400
400⁽⁴⁾
400
Mb/s
DDR2
667
667⁽⁴⁾
625
Mb/s
DDR3
667
667⁽⁴⁾
625
—
Mb/s
LPDDR (Mobile_DDR)
400
400⁽⁴⁾
400
Mb/s
Extended Performance (Requires Extended Memory Controller Block V_CCINT)⁽³⁾
DDR2
800
800⁽⁴⁾
667
—
Mb/s
DDR3
800
800⁽⁴⁾
667
—
Mb/s
Notes:
1. Refer to XAPP1064, Source-Synchronous Serialization and Deserialization (up to 1050 Mb/s).
2. Refer to the Spartan-6 FPGA Memory Controller User Guide
3. Extended Memory Controller block performance for DDR2 and DDR3 can be achieved using the extended MCB performance V_CCINT range
from Table 2.
4. The -3N speed grade does not support a Memory Controller block.
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
16