DS162 Datasheet, PDF (38/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Input/Output Delay Switching Characteristics
Table 38: IODELAY2 Switching Characteristics
Symbol
Description
Speed Grade
Units
-4
-3
-2
-1L
T_{IODCCK_CAL} / T_{IODCKC_CAL}
CAL pin Setup/Hold with respect to CK
0.28 0.33 0.48 0.57 ns
–0.13 –0.13 –0.13 –0.24
T_{IODCCK_CE} / T_{IODCKC_CE}
CE pin Setup/Hold with respect to CK
0.14 0.17 0.25 0.33 ns
–0.03 –0.03 –0.02 0.01
T_{IODCCK_INC}/ T_{IODCKC_INC}
INC pin Setup/Hold with respect to CK
0.10 0.12 0.18 0.23 ns
0.02 0.03 0.06 0.11
T_{IODCCK_RST}/ T_{IODCKC_RST}
T_TAP1(2)
T_TAP2
T_TAP3
T_TAP4
T_TAP5
T_TAP6
T_TAP7
T_TAP8
F_MINCAL
RST pin Setup/Hold with respect to CK
Maximum tap 1 delay
Maximum tap 2 delay
Maximum tap 3 delay
Maximum tap 4 delay
Maximum tap 5 delay
Maximum tap 6 delay
Maximum tap 7 delay
Maximum tap 8 delay
Minimum allowed bit rate for calibration in variable
mode: VARIABLE_FROM_ZERO,
VARIABLE_FROM_HALF_MAX, and
DIFF_PHASE_DETECTOR.
0.12
–0.02
8
40
95
108
171
207
212
292
188
0.15
–0.02
14
66
120
141
194
249
276
341
188
0.22
–0.01
16
77
140
166
231
292
343
424
188
0.28 ns
0.02
ps
ps
ps
ps
ps
ps
ps
ps
Mb/s
T_{IODDO_IDATAIN}
T_{IODDO_ODATAIN}
Propagation delay through IODELAY2
Propagation delay through IODELAY2
Note 1 Note 1 Note 1 Note 1
Note 1 Note 1 Note 1 Note 1
Notes:
1. Delay depends on IODELAY2 tap setting. See TRACE report for actual values.
2. Maximum delay = integer (number of taps/8) × T_TAP8 + T_TAPn (where n equals the remainder). For minimum delay consult the TRACE setup and hold
report. Minimum delay is greater than 30% of the maximum delay.
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
38