DS162 Datasheet, PDF (15/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 22: GTP Transceiver Transmitter Switching Characteristics
Symbol
Description
Condition
Min
Typ
Max
T_RTX
T_FTX
T_LLSKEW
V_TXOOBVDPP
T_{TXOOBTRANSITION}
T_J3.125
D_J3.125
T_J2.5
D_J2.5
T_J1.62
D_J1.62
T_J1.25
D_J1.25
T_J614
D_J614
TX Rise time
TX Fall time
TX lane-to-lane skew⁽¹⁾
Electrical idle amplitude
Electrical idle transition time
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
20%–80%
–
140
–
80%–20%
–
120
–
–
–
400
–
–
20
–
–
50
3.125 Gb/s
–
–
0.35
–
–
0.15
2.5 Gb/s
–
–
0.33
–
–
0.15
1.62 Gb/s
–
–
0.20
–
–
0.10
1.25 Gb/s
–
–
0.20
–
–
0.10
614 Mb/s
–
–
0.10
–
–
0.05
Notes:
1. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTP transceiver sites.
2. Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1. These values are NOT intended for protocol specific compliance determinations.
Units
ps
ps
ps
mV
ns
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
Table 23: GTP Transceiver Receiver Switching Characteristics
Symbol
Description
Min Typ
T_RXELECIDLE
R_XOOBVDPP
R_XSST
R_XRL
Time for RXELECIDLE to respond to loss or restoration of data
OOB detect threshold peak-to-peak
Receiver spread-spectrum tracking⁽¹⁾
Modulated @ 33 KHz
Run length (CID)
Internal AC capacitor bypassed
CDR 2^nd-order loop disabled
–
75
60
–
–5000 –
–
–
–200 –
R_XPPMTOL
Data/REFCLK PPM offset
PLL_RXDIVSEL_OUT = 1 –2000 –
tolerance
CDR 2^nd-order
loop enabled
PLL_RXDIVSEL_OUT = 2
–2000
–
PLL_RXDIVSEL_OUT = 4 –1000 –
SJ Jitter Tolerance⁽²⁾
JT_SJ_3.125
Sinusoidal Jitter⁽³⁾
JT_SJ_2.5
Sinusoidal Jitter⁽³⁾
JT_SJ_1.62
Sinusoidal Jitter⁽³⁾
JT_SJ_1.25
Sinusoidal Jitter⁽³⁾
JT_SJ₆₁₄
Sinusoidal Jitter⁽³⁾
SJ Jitter Tolerance with Stressed Eye⁽²⁾⁽⁵⁾
3.125 Gb/s
2.5 Gb/s
1.62 Gb/s
1.25 Gb/s
614 Mb/s
0.4
–
0.4
–
0.5
–
0.5
–
0.5
–
JT_TJSE_3.125
Total Jitter with stressed eye⁽⁴⁾
3.125 Gb/s
0.65 –
JT_SJSE_3.125
JT_TJSE_2.7
Sinusoidal Jitter with stressed eye
Total Jitter with stressed eye⁽⁴⁾
3.125 Gb/s
2.7 Gb/s
0.1
–
0.65 –
JT_SJSE_2.7
Sinusoidal Jitter with stressed eye
2.7 Gb/s
0.1
–
Notes:
1. Using PLL_RXDIVSEL_OUT = 1, 2, and 4.
2. All jitter values are based on a Bit Error Ratio of 1e^–12.
3. Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter.
4. Composed of 0.37 UI DJ in the form of ISI and 0.18 UI RJ.
5. Measured using PRBS7 data pattern.
Max
–
150
0
150
200
2000
2000
1000
Units
ns
mV
ppm
UI
ppm
ppm
ppm
ppm
–
UI
–
UI
–
UI
–
UI
–
UI
–
UI
–
UI
–
UI
–
UI
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
15