DS162 Datasheet, PDF (31/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 33: SSO Limit per V_CCO/GND Pair (Cont’d)
V_CCO
I/O Standard
Drive Slew
LVCMOS18, LVCMOS18_JEDEC
1.8V
HSTL_I_18
HSTL_II_18
HSTL_III_18
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
MOBILE_DDR ⁽³⁾
DIFF_MOBILE_DDR ⁽³⁾
SSTL_18_I ⁽³⁾
SSTL_18_II ⁽³⁾
DIFF_SSTL_18_I ⁽³⁾
DIFF_SSTL_18_II ⁽³⁾
Fast
2
Slow
QuietIO
Fast
4
Slow
QuietIO
Fast
6
Slow
QuietIO
Fast
8
Slow
QuietIO
Fast
12 Slow
QuietIO
Fast
16 Slow
QuietIO
Fast
24 Slow
QuietIO
SSO Limit per V_CCO/GND Pair
All TQG144, CPG196,
CSG225, FT(G)256, and
LX devices in CSG324
All CSG484, FG(G)484,
FG(G)676, FG(G)900, and
LXT devices in CSG324
Bank 0/2
Bank 1/3
Bank 0/2 Bank 1/3/4/5
39
46
39
47
65
75
65
74
80
80
80
85
22
25
22
25
38
36
38
29
45
40
45
35
16
18
16
17
27
25
27
19
30
28
30
23
13
15
13
14
16
18
16
16
25
22
25
18
5
7
5
5
7
8
7
6
11
10
11
8
4
5
4
4
7
8
7
5
11
10
11
8
N/A
5
N/A
3
N/A
8
N/A
8
N/A
10
N/A
8
9
10
9
9
N/A
5
N/A
6
9
10
9
11
27
30
27
27
N/A
15
N/A
18
27
30
27
33
12
14
12
14
36
42
36
42
9
10
9
10
N/A
5
N/A
4
27
30
27
30
N/A
15
N/A
12
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
31