DS162 Datasheet, PDF (14/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 20: GTP Transceiver Reference Clock Switching Characteristics
Symbol
Description
Conditions
F_GCLK
T_RCLK
T_FCLK
T_DCREF
T_LOCK
T_PHASE
Reference clock frequency range
Reference clock rise time
20% – 80%
Reference clock fall time
80% – 20%
Reference clock duty cycle
Transceiver PLL only
Clock recovery frequency acquisition Initial PLL lock
time
Clock recovery phase acquisition time Lock to data after PLL has locked to
the reference clock
X-Ref Target - Figure 3
80%
T_RCLK
All LXT Speed Grades
Min
Typ
Max
60
–
160
–
200
–
–
200
–
45
50
55
–
–
1
–
–
200
Units
MHz
ps
ps
%
ms
µs
20%
T_FCLK
ds162_05_042109
Figure 3: Reference Clock Timing Parameters
Table 21: GTP Transceiver User Clock Switching Characteristics⁽¹⁾
Symbol
Description
F_TXOUT
F_RXREC
T_RX
T_RX2
TXOUTCLK maximum frequency
RXRECCLK maximum frequency
RXUSRCLK maximum frequency
RXUSRCLK2 maximum frequency
T_TX
T_TX2
TXUSRCLK maximum frequency
TXUSRCLK2 maximum frequency
Conditions
1 byte interface
2 byte interface
4 byte interface
1 byte interface
2 byte interface
4 byte interface
-4
320
320
320
156.25
160
80
320
156.25
160
80
Notes:
1. Clocking must be implemented as described in the Spartan-6 FPGA GTP Transceivers User Guide.
Speed Grade
-3
-2
320
270
320
270
320
270
156.25 125
160
125
80
67.5
320
270
156.25 125
160
125
80
67.5
Units
-1L
N/A MHz
N/A MHz
N/A MHz
N/A MHz
N/A MHz
N/A MHz
N/A MHz
N/A MHz
N/A MHz
N/A MHz
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
14