DS162 Datasheet, PDF (48/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
PLL Switching Characteristics
Table 50: PLL Specification
Symbol
Description
Device⁽¹⁾
Speed Grade
Units
-4
-3
-2
-1L
F_INMAX
Maximum Input Clock Frequency
from I/O Clock
LX Family
LXT Family
N/A 525 450
MHz
540 525 450 N/A MHz
F_INMIN
F_INJITTER
F_INDUTY
Maximum Input Clock Frequency
from Global Clock
LX Family
LXT Family
Minimum Input Clock Frequency
LX Family
LXT Family
Maximum Input Clock Period Jitter
All
Allowable Input Duty Cycle: 19—199 MHz All
Allowable Input Duty Cycle: 200—299 MHz All
N/A 400 375
MHz
400 400 375 N/A MHz
N/A
19
19
MHz
19
19
19
N/A MHz
<20% of clock input period or 1 ns Max
25/75
%
35/65
%
F_VCOMIN
Allowable Input Duty Cycle: > 300 MHz
Minimum PLL VCO Frequency
All
LX Family
LXT Family
45/55
%
N/A 400 400 400 MHz
400 400 400 N/A MHz
F_VCOMAX
F_BANDWIDTH
T_STAPHAOFFSET
T_OUTJITTER
T_OUTDUTY
T_LOCKMAX
F_OUTMAX
Maximum PLL VCO Frequency
Low PLL Bandwidth at Typical⁽³⁾
High PLL Bandwidth at Typical⁽³⁾
Static Phase Offset of the PLL Outputs
PLL Output Jitter⁽³⁾
PLL Output Clock Duty Cycle Precision⁽⁴⁾
PLL Maximum Lock Time
PLL Maximum Output Frequency for
BUFGMUX
LX Family
LXT Family
All
All
All
All
All
All
LX Family
LXT Family
N/A
1080
1
4
0.12
0.15
100
N/A
400
1050
1050
1
4
0.12
0.15
100
400
400
1000
1000
1
4
0.12
Note 2
0.20
100
375
375
1000
N/A
1
4
100
N/A
MHz
MHz
MHz
MHz
ns
ns
µs
MHz
MHz
F_OUTMAX
F_OUTMIN
T_EXTFDVAR
RST_MINPULSE
F_PFDMAX(5)
F_PFDMIN
T_FBDELAY
PLL Maximum Output Frequency for
BUFPLL
PLL Minimum Output Frequency⁽⁵⁾
External Clock Feedback Variation
Minimum Reset Pulse Width
Maximum Frequency at the Phase
Frequency Detector
Minimum Frequency at the Phase
Frequency Detector
Maximum Delay in the Feedback Path
LX Family
LXT Family
All
All
All
LX Family
LXT Family
LX Family
LXT Family
All
N/A 1050 950
MHz
1080 1050 950 N/A MHz
3.125 3.125 3.125 3.125 MHz
< 20% of clock input period or 1 ns Max
5
5
5
5
ns
N/A 500 400
MHz
500 500 400 N/A MHz
N/A
19
19
MHz
19
19
19
N/A MHz
3 ns Max or one CLKIN cycle
Notes:
1. LX devices are not available with a -4 speed grade; LXT devices are not available with a -1L speed grade.
2. Values for this parameter are available in the Clocking Wizard.
3. The PLL does not filter typical spread spectrum input clocks because they are usually far below the bandwidth filter frequencies.
4. Includes global clock buffer.
5. Calculated as F_VCO/128 assuming output duty cycle is 50%.
6. When using CLK_FEEDBACK = CLKOUT0 with BUFIO2 feedback, the feedback frequency will be higher than the phase frequency detector
frequency. F_PFDMAX = F_CLKFB / CLKFBOUT_MULT
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
48