DS162 Datasheet, PDF (43/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 43: DSP48A1 Switching Characteristics (Cont’d)
Symbol
Description
Pre-
adder
Multiplier
Post-
adder
-4
Speed Grade
-3
-2
Units
-1L
Clock to Out from Output Register Clock to Output Pin
T_{DSPCKO_P_PREG}
CLK (PREG) to P output
N/A
N/A
Clock to Out from Pipeline Register Clock to Output Pins
N/A 1.20 1.34 1.34 1.90 ns
T_{DSPCKO_P_MREG}
CLK (MREG) to P output
N/A
N/A
Clock to Out from Input Register Clock to Output Pins
Yes 3.38 3.95 4.19 5.83 ns
T_{DSPCKO_P_A1REG}
CLK (A1REG) to P output N/A
Yes
T_{DSPCKO_P_B1REG}
CLK (B1REG) to P output N/A
Yes
T_{DSPCKO_P_CREG}
CLK (CREG) to P output
N/A
N/A
T_{DSPCKO_P_DREG}
CLK (DREG) to P output
Yes
Yes
Combinatorial Delays from Input Pins to Output Pins
Yes 5.02 5.87 6.80 9.65 ns
Yes 5.02 5.87 6.79 9.63 ns
Yes 3.12 3.64 3.70 5.24 ns
Yes 6.77 7.92 9.06 12.53 ns
T_{DSPDO_A_P}
A input to P output
N/A
No
N/A
Yes
Yes 2.85 3.33 3.41 4.73 ns
No
3.35 3.93 4.83 6.74 ns
N/A
Yes
Yes 4.56 5.22 6.38 8.94 ns
T_{DSPDO_B_P}
B input to P output
Yes
No
Yes
Yes
No
3.22 3.76 3.91 5.55 ns
No
6.01 6.54 6.88 9.76 ns
Yes
Yes
Yes 6.27 7.34 8.43 11.96 ns
T_{DSPDO_C_P}
T_{DSPDO_D_P}
T_{DSPDO_OPMODE_P}
C input to P output
N/A
N/A
D input to P output
Yes
Yes
OPMODE input to P output Yes
Yes
No
Yes
Yes 2.69 3.15 3.30 4.68 ns
Yes 6.31 7.38 8.32 11.81 ns
Yes 6.43 7.52 8.35 11.84 ns
Yes 4.84 5.66 6.52 9.25 ns
No
No
Yes 3.11 3.49 3.55 5.03 ns
Maximum Frequency
F_MAX
All registers used
Yes
Yes
Yes
390 333 302 213 MHz
Notes:
1. A Yes signifies that the component is in the path. A No signifies that the component is being bypassed. N/A signifies not applicable because no path
exists.
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
43