DS162 Datasheet, PDF(25/73 Page) Xilinx, Inc – Advance Product Specification

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DS162 Datasheet, PDF (25/73 Pages) Xilinx, Inc – Advance Product Specification

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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

I/O Standard Adjustment Measurement Methodology

Input Delay Measurements

Table 30 shows the test setup parameters used for measuring input delay.

Table 30: Input Delay Measurement Methodology

Description

LVTTL (Low-Voltage Transistor-Transistor Logic)

I/O Standard Attribute

LVTTL

VL(1)

VH(1)

3.0

VMEAS(3)(4) VREF(2)(4)

1.4

LVCMOS (Low-Voltage CMOS), 3.3V

LVCMOS33

3.3

1.65

LVCMOS, 2.5V

LVCMOS25

2.5

1.25

LVCMOS, 1.8V

LVCMOS18

1.8

0.9

LVCMOS, 1.5V

LVCMOS15

1.5

0.75

LVCMOS, 1.2V

LVCMOS12

1.2

0.6

PCI (Peripheral Component Interface),

33 MHz and 66 MHz, 3.3V

PCI33_3, PCI66_3

Per PCI Specification

HSTL (High-Speed Transceiver Logic),

Class I & II

HSTL_I, HSTL_II

VREF â 0.5 VREF + 0.5

VREF

0.75

HSTL, Class III

HSTL, Class I & II, 1.8V

HSTL, Class III 1.8V

SSTL (Stub Terminated Transceiver Logic),

Class I & II, 3.3V

HSTL_III

HSTL_I_18, HSTL_II_18

HSTL_III_18

SSTL3_I, SSTL3_II

VREF â 0.5

VREF â 0.75

VREF + 0.5

VREF + 0.75

VREF

0.90

1.1

1.5

SSTL, Class I & II, 2.5V

SSTL2_I, SSTL2_II

VREF â 0.75 VREF + 0.75

VREF

1.25

SSTL, Class I & II, 1.8V

SSTL18_I, SSTL18_II

VREF â 0.5 VREF + 0.5

VREF

0.90

SSTL, Class II, 1.5V

LVDS (Low-Voltage Differential Signaling),

2.5V & 3.3V

SSTL15_II

LVDS_25, LVDS_33

VREF â 0.2 VREF + 0.2

1.25 â 0.125 1.25 + 0.125

VREF

0(5)

0.75

LVPECL (Low-Voltage Positive Emitter-Coupled

LVPECL_25, LVPECL_33 1.2 â 0.3

1.2 â 0.3

0(5)

Logic), 2.5V & 3.3V

BLVDS (Bus LVDS), 2.5V

BLVDS_25

1.3 â 0.125 1.3 + 0.125

0(5)

Mini-LVDS, 2.5V & 3.3V

MINI_LVDS_25,

MINI_LVDS_33

1.2 â 0.125 1.2 + 0.125

0(5)

RSDS (Reduced Swing Differential Signaling),

RSDS_25, RSDS_33

1.2 â 0.1

1.2 + 0.1

0(5)

2.5V & 3.3V

TMDS (Transition Minimized Differential Signaling), TMDS_33

3.3V

3.0 â 0.1

3.0 + 0.1

0(5)

PPDS (Point-to-Point Differential Signaling,

2.5V & 3.3V

PPDS_25, PPDS_33

1.25 â 0.1 1.25 + 0.1

0(5)

Notes:

1. Input waveform switches between VL and VH.

2. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values

listed are typical.

3. Input voltage level from which measurement starts.

4. This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 4.

5. The value given is the differential input voltage.

DS162 (v1.9) August 23, 2010

www.xilinx.com

Advance Product Specification

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