English
Language : 

DS162 Datasheet, PDF (45/73 Pages) Xilinx, Inc – Advance Product Specification
◁
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Configuration Switching Characteristics
Table 46: Configuration Switching Characteristics(1)
Symbol
Description
Speed Grade
Units
-4
-3
-2
-1L
Power-up Timing Characteristics
TPL(2)
TPOR(2)
PROGRAM_B Latency
Power-on-Reset
TPROGRAM
PROGRAM_B Pulse Width
Slave Serial Mode Programming Switching
4
4
4
5
ms, Max
5/40
5/40
5/40
5/40 ms, Min/Max
500
500
500
500
ns, Min
TDCCK/TCCKD
DIN Setup/Hold, slave mode
TCCO
CCLK to DOUT
FSCCK
Slave mode external CCLK
Slave SelectMAP Mode Programming Switching
6.0/1.0
12
80
6.0/1.0
12
80
6.0/1.0
12
80
8.0/2.0
17
50
ns, Min
ns, Max
MHz, Max
TSMDCCK/TSMCCKD
TSMCSCCK/TSMCCKCS
TSMCCKW/TSMWCCK
TSMCKCSO
TSMCO
TSMCKBY
FSMCCK
SelectMAP Data Setup/Hold
CSI_B Setup/Hold
RDWR_B Setup/Hold
CSO_B clock to out
CCLK to DATA out in readback
CCLK to BUSY out in readback
Maximum CCLK frequency (XC6SLX4,
XC6SLX9, XC6SLX16, XC6SLX25,
XC6SLX25T, XC6SLX45, XC6SLX45T,
XC6SLX75, and XC6SLX75T only)
Maximum CCLK frequency
(XC6SLX100, XC6SLX100T,
XC6SLX150, and XC6SLX150T only)
6.0/1.0 6.0/1.0 6.0/1.0 8.0/2.0
7.0/0.0 7.0/0.0 7.0/0.0 9.0/2.0
17.0/1.0 17.0/1.0 17.0/1.0 27.0/2.0
16
16
16
26
13
13
13
25
12
12
12
17
50
50
50
25
40
40
40
20
ns, Min
ns, Min
ns, Min
ns, Min
ns, Max
ns, Max
MHz, Max
MHz, Max
FRBCCK
Maximum Readback CCLK frequency
20
20
20
(XC6SLX4, XC6SLX9, XC6SLX16,
XC6SLX25, XC6SLX25T, XC6SLX45,
XC6SLX45T, XC6SLX75, and
XC6SLX75T only)
4
MHz, Max
Maximum Readback CCLK frequency
12
12
12
(XC6SLX100, XC6SLX100T,
XC6SLX150, and XC6SLX150T only)
4
MHz, Max
Boundary-Scan Port Timing Specifications
TTAPTCK
TTCKTAP
TTCKTDO
TTCKH
TTCKL
FTCK
TMS and TDI Setup time before TCK
10
10
10
17
ns, Min
TMS and TDI Hold time after TCK
5.5
5.5
5.5
5.5
ns, Min
TCK falling edge to TDO output valid
6.5
6.5
6.5
8
ns, Max
TCK clock minimum High time
12
12
12
21
ns, Min
TCK clock minimum Low time
12
12
12
21
ns, Min
Maximum configuration TCK clock
frequency
33
33
33
18 MHz, Max
FTCKB
Maximum boundary-scan TCK clock
frequency
33
33
33
18 MHz, Max
FTCKAES
Maximum AES key TCK clock frequency 2
2
2
2
MHz, Max
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
45
 ▷