DS162 Datasheet, PDF (67/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 74: Global Clock Setup and Hold With DCM and PLL in Source-Synchronous Mode
Symbol
Description
Device
Speed Grade
Units
-4
-3
-2
-1L
Example Data Input Set-Up and Hold Times Relative to a Forwarded Clock Input Pin,⁽¹⁾ Using DCM, PLL, and Global Clock Buffer. For
situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values
shown in IOB Switching Characteristics, page 19.
T_{PSDCMPLL_0}/
No Delay Global Clock and IFF⁽²⁾ with DCM XC6SLX4
N/A
1.11/
1.21/
ns
T_{PHDCMPLL_0}
in Source-Synchronous Mode and PLL in
1.38
1.38
DCM2PLL Mode.
XC6SLX9
N/A
1.10/
1.20/
ns
1.38
1.39
XC6SLX16
N/A
0.83/
0.83/
ns
1.12
1.21
XC6SLX25
N/A
0.76/
0.84/
ns
1.11
1.18
XC6SLX25T
0.84/
1.02
0.84/
1.11
0.84/
1.18
N/A
ns
XC6SLX45
N/A
0.65/
0.71/
ns
1.04
1.12
XC6SLX45T
0.68/
1.00
0.68/
1.04
0.71/
1.12
N/A
ns
XC6SLX75
N/A
0.88/
0.94/
ns
1.06
1.14
XC6SLX75T
0.89/
1.03
0.89/
1.06
0.94/
1.14
N/A
ns
XC6SLX100
N/A
0.56/
0.61/
ns
1.10
1.17
XC6SLX100T
0.63/
1.10
0.63/
1.10
0.63/
1.17
N/A
ns
XC6SLX150
N/A
0.47/
0.53/
ns
1.28
1.28
XC6SLX150T
0.50/
1.28
0.50/
1.28
0.52/
1.28
N/A
ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock
input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using
the fastest process, lowest temperature, and highest voltage. The timing values were measured using the fine-phase adjustment feature of the DCM.
These measurements include CMT jitter; DCM CLK0 driving PLL, PLL CLKOUT0 driving BUFG. Package skew is not included in these
measurements.
2. IFF = Input Flip-Flop
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
67