DS162 Datasheet, PDF (10/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 10: Differential I/O Standard DC Input and Output Levels
I/O Standard
V_ID
mV, mV,
Min Max
V_ICM
V, Min V, Max
V_OD
mV, Min
mV,
Max
V_OCM
V, Min
V, Max
V_OH
V, Min
V_OL
V, Max
LVDS_33
100 600
0.3
2.35
247
454
1.125
1.375
–
–
LVDS_25
100 600
0.3
2.35
247
454
1.125
1.375
–
–
BLVDS_25
MINI_LVDS_33
100
–
0.3
2.35
240
460
200 600
0.3
1.95
300
600
Typical 50% V_CCO
1.0
1.4
–
–
–
–
MINI_LVDS_25
LVPECL_33
200 600
0.3
1.95
300
600
100 1000 0.3
2.8⁽¹⁾
1.0
1.4
Inputs only
–
–
LVPECL_25
100 1000 0.3
1.95
Inputs only
RSDS_33
100
–
0.3
1.5
100
400
1.0
1.4
–
–
RSDS_25
TMDS_33
PPDS_33
100
–
0.3
1.5
100
400
1.0
1.4
–
–
150 1200 2.7 3.23⁽¹⁾ 400
800 V_CCO – 0.405 V_CCO – 0.190
–
–
100 400
0.2
2.3
100
400
0.5
1.4
–
–
PPDS_25
100 400
0.2
2.3
100
400
0.5
1.4
–
–
DISPLAY_PORT
190 1260 0.3
2.35
–
–
DIFF_MOBILE_DDR 100
–
0.78 1.02
–
–
DIFF_HSTL_I
100
–
0.68
0.9
–
–
DIFF_HSTL_II
100
–
0.68
0.9
–
–
DIFF_HSTL_III
100
–
0.68
0.9
–
–
DIFF_HSTL_I_18
100
–
0.8
1.1
–
–
DIFF_HSTL_II_18
100
–
0.8
1.1
–
–
DIFF_HSTL_III_18 100
–
0.8
1.1
–
–
DIFF_SSTL3_I
100
–
1.0
1.9
–
–
DIFF_SSTL3_II
100
–
1.0
1.9
–
–
DIFF_SSTL2_I
100
–
1.0
1.5
–
–
DIFF_SSTL2_II
100
–
1.0
1.5
–
–
DIFF_SSTL18_I
100
–
0.7
1.1
–
–
DIFF_SSTL18_II
100
–
0.7
1.1
–
–
DIFF_SSTL15_II
100
–
0.55 0.95
–
–
Typical 50% V_CCO
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
90% V_CCO 10% V_CCO
V_CCO – 0.4
0.4
V_CCO – 0.4
0.4
V_CCO – 0.4
0.4
V_CCO – 0.4
0.4
V_CCO – 0.4
0.4
V_CCO – 0.4
0.4
V_TT + 0.6 V_TT – 0.6
V_TT + 0.8 V_TT – 0.8
V_TT + 0.61 V_TT – 0.61
V_TT + 0.81 V_TT – 0.81
V_TT + 0.47 V_TT – 0.47
V_TT + 0.6 V_TT – 0.6
V_TT + 0.4 V_TT – 0.4
Notes:
1. LVPECL_33 and TMDS_33 maximum V_ICM is the lower of V (maximum) or V_CCAUX – (V_ID/2)
eFUSE Read Endurance
Table 11 lists the minimum guaranteed number of read cycle operations for Device DNA and for the AES eFUSE key. For
more information, see the Spartan-6 FPGA Configuration User Guide.
Table 11: eFUSE Read Endurance
Symbol
Description
DNA_CYCLES
AES_CYCLES
Number of DNA_PORT READ operations or JTAG ISC_DNA read
command operations. Unaffected by SHIFT operations.
Number of JTAG FUSE_KEY or FUSE_CNTL read command
operations. Unaffected by SHIFT operations.
Speed Grade
Units
-4
-3
-2
-1L ^(Min)
30,000,000
Read
Cycles
30,000,000
Read
Cycles
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
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