DS162 Datasheet, PDF (66/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 73: Global Clock Setup and Hold With DCM and PLL in System-Synchronous Mode
Symbol
Description
Device
Speed Grade
-4
-3
-2
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.⁽¹⁾
T_PSDCMPLL/
T_PHDCMPLL
No Delay Global Clock and IFF⁽²⁾ with
DCM in System-Synchronous Mode and
PLL in DCM2PLL Mode.
XC6SLX4
XC6SLX9
N/A
2.06/
2.30/
0.87
0.87
N/A
2.05/
2.29/
0.88
0.88
XC6SLX16
N/A
1.49/
1.62/
0.18
0.18
XC6SLX25
N/A
1.65/
1.83/
0.42
0.42
XC6SLX25T
1.69/
0.42
1.69/
0.42
1.83/
0.42
XC6SLX45
N/A
1.59/
1.75/
0.39
0.39
XC6SLX45T
1.57/
0.39
1.59/
0.39
1.75/
0.39
XC6SLX75
N/A
1.80/
1.99/
0.41
0.41
XC6SLX75T
1.74/
0.41
1.80/
0.41
1.99/
0.41
XC6SLX100
N/A
1.46/
1.64/
0.51
0.51
XC6SLX100T
1.46/
0.51
1.46/
0.51
1.64/
0.51
XC6SLX150
N/A
1.40/
1.55/
0.69
0.69
XC6SLX150T
1.35/
0.69
1.40/
0.69
1.55/
0.69
Units
-1L
ns
ns
ns
ns
N/A
ns
ns
N/A
ns
ns
N/A
ns
ns
N/A
ns
ns
N/A
ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock
input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using
the fastest process, lowest temperature, and highest voltage. These measurements include CMT jitter; DCM CLK0 driving PLL, PLL CLKOUT0
driving BUFG.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
66