DS162 Datasheet, PDF (47/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Clock Buffers and Networks
Table 47: Global Clock Switching Characteristics
Symbol
Description
Devices
T_GSI
T_GIO
Maximum Frequency
F_MAX
S pin Setup to I0/I1 inputs LX Family
LXT Family
BUFGMUX delay from
I0/I1 to O
LX Family
LXT Family
LX Family
Global clock tree (BUFG)
LXT Family
Table 48: Input/Output Clock Switching Characteristics (BUFIO2)
Symbol
Description
Devices
T_{BUFCKO_O}
Maximum Frequency
F_MAX
Clock to out delay from I to O LX Family
LXT Family
I/O clock tree (BUFIO2)
LX Family
LXT Family
Table 49: Input/Output Clock Switching Characteristics (BUFPLL)
Symbol
Description
Devices
Maximum Frequency
F_MAX
BUFPLL clock tree (BUFPLL) LX Family
LXT Family
Speed Grade
Units
-4
-3
-2
-1L
N/A 0.31 0.48 0.60 ns
0.25 0.31 0.48 N/A
ns
N/A 0.21 0.21
ns
0.21 0.21 0.21 N/A
ns
N/A 400 375
MHz
400 400 375 N/A MHz
Speed Grade
Units
-4
-3
-2
-1L
N/A 0.82 1.09 1.80 ns
0.67 0.82 1.09 N/A
ns
N/A 525 500
MHz
540 525 500 N/A MHz
Speed Grade
Units
-4
-3
-2
-1L
N/A 1050 950
1080 1050 950
MHz
N/A MHz
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
47