DS162 Datasheet, PDF (42/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DSP48A1 Switching Characteristics
Table 43: DSP48A1 Switching Characteristics
Symbol
Description
Pre-
adder
Multiplier
Post-
adder
Setup and Hold Times of Data/Control Pins to the Input Register Clock
T_{DSPDCK_A_A1REG}/
T_{DSPCKD_A_A1REG}
A input to A1 register CLK N/A
N/A
N/A
T_{DSPDCK_D_B1REG}/
T_{DSPCKD_D_B1REG}
D input to B1 register CLK Yes
N/A
N/A
T_{DSPDCK_C_CREG}/
T_{DSPCKD_C_CREG}
C input to C register CLK N/A
N/A
N/A
T_{DSPDCK_D_DREG}/
T_{DSPCKD_D_DREG}
D input to D register CLK N/A
N/A
N/A
T_{DSPDCK_OPMODE_B1REG}/
T_{DSPCKD_OPMODE_B1REG}
OPMODE input to B1
register CLK
Yes
N/A
N/A
T_{DSPDCK_OPMODE_OPMODEREG}/ OPMODE input to
N/A
N/A
N/A
T_{DSPCKD_OPMODE_OPMODEREG} OPMODE register CLK
Setup and Hold Times of Data Pins to the Pipeline Register Clock
T_{DSPDCK_A_MREG}/
T_{DSPCKD_A_MREG}
T_{DSPDCK_B_MREG}/
T_{DSPCKD_B_MREG}
T_{DSPDCK_D_MREG}/
T_{DSPCKD_D_MREG}
T_{DSPDCK_OPMODE_MREG}/
T_{DSPCKD_OPMODE_MREG}
A input to M register CLK N/A
Yes
N/A
B input to M register CLK Yes
Yes
N/A
D input to M register CLK Yes
Yes
N/A
OPMODE to M register
Yes
Yes
N/A
CLK
No
Yes
N/A
Setup and Hold Times of Data/Control Pins to the Output Register Clock
T_{DSPDCK_A_PREG}/
T_{DSPCKD_A_PREG}
T_{DSPDCK_B_PREG}/
T_{DSPCKD_B_PREG}
A input to P register CLK
N/A
Yes
Yes
B input to P register CLK
Yes
Yes
Yes
No
Yes
Yes
T_{DSPDCK_C_PREG}/
T_{DSPCKD_C_PREG}
T_{DSPDCK_D_PREG}/
T_{DSPCKD_D_PREG}
T_{DSPDCK_OPMODE_PREG}/
T_{DSPCKD_OPMODE_PREG}
C input to P register CLK N/A
N/A
Yes
D input to P register CLK Yes
Yes
Yes
OPMODE input to P
register CLK
Yes
Yes
Yes
No
Yes
Yes
No
No
Yes
Speed Grade
Units
-4
-3
-2
-1L
0.15 0.17 0.23 0.32 ns
0.09 0.09 0.09 0.09
1.90 1.95 1.99 2.82 ns
–0.07 –0.07 –0.07 –0.07
0.11 0.13 0.17 0.24 ns
0.15 0.15 0.15 0.09
0.09 0.10 0.14 0.19 ns
0.15 0.15 0.15 0.12
1.97 2.00 2.01 2.85 ns
0.01 0.01 0.01 0.01
0.18 0.21 0.28 0.40 ns
0.12 0.12 0.26 0.12
3.06 3.51 3.71 3.97 ns
–0.40 –0.40 –0.40 –0.40
3.96 4.58 5.28 7.00 ns
–0.68 –0.68 –0.68 –0.68
4.23 4.80 4.82 6.84 ns
–0.56 –0.56 –0.56 –0.56
4.18 4.80 4.85 6.88 ns
–0.48 –0.48 –0.48 –0.48
2.37 2.70 3.02 4.28 ns
–0.48 –0.48 –0.48 –0.48
4.32 5.06 5.38 7.52 ns
–0.76 –0.76 –0.76 –0.76
5.87 6.87 7.87 10.55 ns
–0.59 –0.59 –0.59 –0.59
4.14 4.68 6.16 8.12 ns
–0.93 –0.93 –0.93 –0.93
2.20 2.25 2.30 3.27 ns
–0.23 –0.23 –0.23 –0.23
5.90 6.91 7.32 10.39 ns
–0.92 –0.92 –0.92 –0.92
6.21 7.27 7.35 10.43 ns
–0.84 –0.84 –0.84 –0.84
1.69 1.98 2.55 3.62 ns
–0.87 –0.87 –0.87 –0.87
2.09 2.30 2.67 3.79 ns
–0.22 –0.22 –0.22 –0.22
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
42