DS162 Datasheet, PDF (57/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 62: Global Clock Input to Output Delay With DCM in System-Synchronous Mode
Symbol
Description
Device
Speed Grade
Units
-4
-3
-2
-1L
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in System-Synchronous Mode.
T_ICKOFDCM
Global Clock and OUTFF with DCM
XC6SLX4
N/A
4.50
5.32
ns
XC6SLX9
N/A
4.50
5.31
ns
XC6SLX16
N/A
4.57
5.34
ns
XC6SLX25
N/A
4.18
4.59
ns
XC6SLX25T
3.95
4.18
4.59
N/A
ns
XC6SLX45
N/A
4.70
5.50
ns
XC6SLX45T
4.37
4.70
5.50
N/A
ns
XC6SLX75
N/A
4.23
4.77
ns
XC6SLX75T
3.90
4.23
4.77
N/A
ns
XC6SLX100
N/A
4.16
4.66
ns
XC6SLX100T
3.90
4.16
4.66
N/A
ns
XC6SLX150
N/A
4.33
4.83
ns
XC6SLX150T
4.03
4.33
4.83
N/A
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible
IOB and CLB flip-flops are clocked by the global clock net.
2. DCM output jitter is already included in the timing calculation.
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
57