DS162 Datasheet, PDF (44/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 44: Device DNA Interface Port Switching Characteristics
Symbol
Description
T_DNASSU
T_DNASH
T_DNADSU
T_DNADH
Setup time on SHIFT before the rising edge of CLK
Hold time on SHIFT after the rising edge of CLK
Setup time on DIN before the rising edge of CLK
Hold time on DIN after the rising edge of CLK
T_DNARSU
Setup time on READ before the rising edge of CLK
T_DNARH
Hold time on READ after the rising edge of CLK
T_DNADCKO
Clock-to-output delay on DOUT after rising edge of CLK
T_DNACLKF(2)
T_DNACLKL
T_DNACLKH
CLK frequency
CLK Low time
CLK High time
Notes:
1. The minimum READ pulse width is 8 ns, the maximum READ pulse width is 1 µs.
2. Also applies to TCK when reading DNA through the boundary-scan port.
Speed Grade
-4
-3
-2
-1L
Units
7
ns, Min
1
ns, Min
7
ns, Min
1
ns, Min
7
ns, Min
1,000
ns, Max
1
ns, Min
0.5
ns, Min
6
ns, Max
2
MHz, Max
50
ns, Min
50
ns, Min
Table 45: Suspend Mode Switching Characteristics
Symbol
Description
Min
Entering Suspend Mode
T_{SUSPENDHIGH_AWAKE}
T_{SUSPENDFILTER}
T_{SUSPEND_GWE}
Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter 2.5
Adjustment to SUSPEND pin rising edge parameters when glitch filter enabled 31
Rising edge of SUSPEND pin until FPGA output pins drive their defined
–
SUSPEND constraint behavior (without glitch filter)
T_{SUSPEND_GTS}
Rising edge of SUSPEND pin to write-protect lock on all writable clocked
–
elements (without glitch filter)
T_{SUSPEND_DISABLE}
Rising edge of the SUSPEND pin to FPGA input pins and interconnect
–
disabled (without glitch filter)
Exiting Suspend Mode
T_{SUSPENDLOW_AWAKE}
Falling edge of the SUSPEND pin to rising edge of the AWAKE pin. Does not 7
include DCM or PLL lock time.
T_{SUSPEND_ENABLE}
Falling edge of the SUSPEND pin to FPGA input pins and interconnect re-
7
enabled
T_{AWAKE_GWE1}
Rising edge of the AWAKE pin until write-protect lock released on all writable –
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:1.
T_{AWAKE_GWE512}
Rising edge of the AWAKE pin until write-protect lock released on all writable –
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:512.
T_{AWAKE_GTS1}
Rising edge of the AWAKE pin until outputs return to the behavior described in –
the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:1.
T_{AWAKE_GTS512}
Rising edge of the AWAKE pin until outputs return to the behavior described in –
the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:512.
T_{SCP_AWAKE}
Rising edge of SCP pins to rising edge of AWAKE pin
7
Max Units
14
ns
430
ns
15
ns
15
ns
1500 ns
75
µs
41
µs
80
ns
20.5 µs
80
ns
20.5 µs
75
µs
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
44