DS162 Datasheet, PDF (39/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
CLB Switching Characteristics (SLICEM Only)
Table 39: CLB Switching Characteristics (SLICEM Only)
Symbol
Description
Combinatorial Delays
T_ILO
An – Dn LUT inputs to A to D outputs
An – Dn LUT inputs through F7AMUX/F7BMUX
to AMUX/CMUX output
T_OPAB
An – Dn LUT inputs through F7AMUX or F7BMUX and F8MUX
to BMUX output
T_ITO
T_{TITO_LOGIC}
T_OPCYA
T_OPCYB
T_OPCYC
T_OPCYD
T_AXCY
T_BXCY
T_CXCY
T_DXCY
T_BYP
T_CINA
T_CINB
T_CINC
T_CIND
Sequential Delays
An – Dn LUT inputs through latch to AQ – DQ outputs
An – Dn LUT inputs to AQ – DQ outputs (latch as logic)
An LUT inputs to COUT output
Bn LUT inputs to COUT output
Cn LUT inputs to COUT output
Dn LUT inputs to COUT output
AX input to COUT output
BX input to COUT output
CX input to COUT output
DX input to COUT output
CIN input to COUT output
CIN input to AMUX output
CIN input to BMUX output
CIN input to CMUX output
CIN input to DMUX output
T_CKO
Clock to AQ – DQ outputs
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
T_DICK/T_CKDI
AX – DX input to CLK on A – D flip-flops
T_CECK/T_CKCE
CE input to CLK on A – D flip-flops
T_SRCK/T_CKSR
SR input to CLK on A – D flip-flops
T_CINCK/T_CKCIN
CIN input to CLK on A – D flip-flops
Set/Reset
T_RPW
T_RQ
T_CEO
F_TOG
SR input minimum pulse width
Delay from SR input to AQ – DQ flip-flops
Delay from CE input to AQ – DQ flip-flops
Toggle frequency (for export control)
-4
0.21
0.37
0.37
0.82
0.82
0.38
0.38
0.28
0.28
0.21
0.13
0.10
0.09
0.08
0.21
0.30
0.29
0.31
0.45
0.42
0.28
0.31
–0.07
0.34
0.02
0.31
–0.17
0.41
1.81
0.53
862
Speed Grade
-3
-2
0.26 0.38
0.43 0.61
0.46 0.65
0.95 1.28
0.95 1.28
0.48 0.72
0.49 0.71
0.33 0.49
0.35 0.48
0.26 0.40
0.16 0.24
0.12 0.18
0.11 0.14
0.10 0.13
0.22 0.29
0.31 0.46
0.31 0.41
0.32 0.44
0.53 0.64
0.47
0.39
0.37
–0.07
0.42
0.02
0.31
–0.13
0.74
0.54
0.59
–0.07
0.49
0.02
0.49
–0.12
0.48 0.65
1.81 2.50
0.65 0.92
806 667
Units
-1L
0.49 ns, Max
0.80 ns, Max
0.86 ns, Max
1.70 ns, Max
1.70 ns, Max
0.95 ns, Max
0.92 ns, Max
0.67 ns, Max
0.63 ns, Max
0.51 ns, Max
0.35 ns, Max
0.18 ns, Max
0.18 ns, Max
0.11 ns, Max
0.47 ns, Max
0.58 ns, Max
0.59 ns, Max
0.67 ns, Max
0.82 ns, Max
0.99
0.58
0.59
–0.27
0.63
–0.33
0.79
–0.46
ns, Min
ns, Min
ns, Min
ns, Min
1.58 ns, Min
3.05 ns, Max
1.36 ns, Max
MHz
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
39