DS162 Datasheet, PDF (26/73 Pages) Xilinx, Inc – Advance Product Specification

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Output Delay Measurements
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pF) across approximately 4" of FR4
microstrip trace. Standard termination was used for all
testing. The propagation delay of the 4" trace is
characterized separately and subtracted from the final
measurement, and is therefore not included in the
generalized test setups shown in Figure 4 and Figure 5.
X-Ref Target - Figure 4
V_REF
FPGA Output
R_REF
V_MEAS
(voltage level when taking
delay measurement)
C_REF
(probe capacitance)
ds162_06_011309
Figure 4: Single-Ended Test Setup
X-Ref Target - Figure 5
FPGA Output
+
C_REF
R_REF V_MEAS
–
ds162_07_011309
Figure 5: Differential Test Setup
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it.
Parameters V_REF, R_REF, C_REF, and V_MEAS fully describe
the test conditions for each I/O standard. The most accurate
prediction of propagation delay in any given application can
be obtained through IBIS simulation, using the following
method:
1. Simulate the output driver of choice into the generalized
test setup, using values from Table 31.
2. Record the time to V_MEAS.
3. Simulate the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
4. Record the time to V_MEAS.
5. Compare the results of steps 2 and 4. The increase or
decrease in delay yields the actual propagation delay of
the PCB trace.
Table 31: Output Delay Measurement Methodology
Description
I/O Standard
Attribute
R_REF C_REF⁽¹⁾ V_MEAS V_REF
(Ω) (pF)
(V) (V)
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVTTL (all)
1M
0
1.4
0
LVCMOS (Low-Voltage CMOS), 3.3V
LVCMOS33
1M
0
1.65
0
LVCMOS, 2.5V
LVCMOS25
1M
0
1.25
0
LVCMOS, 1.8V
LVCMOS18
1M
0
0.9
0
LVCMOS, 1.5V
LVCMOS15
1M
0
0.75
0
LVCMOS, 1.2V
PCI (Peripheral Component Interface)
33 MHz and 66 MHz, 3.3V
LVCMOS12
PCI33_3, PCI66_3 (rising edge)
PCI33_3, PCI66_3 (falling edge)
1M
0
0.75
0
25
10 ⁽²⁾
0.94
0
25
10⁽²⁾
2.03
3.3
HSTL (High-Speed Transceiver Logic), Class I
HSTL, Class II
HSTL, Class III
HSTL_I
HSTL_II
HSTL_III
50
0
V_REF 0.75
25
0
V_REF 0.75
50
0
0.9
1.5
HSTL, Class I, 1.8V
HSTL, Class II, 1.8V
HSTL, Class III, 1.8V
HSTL_I_18
HSTL_II_18
HSTL_III_18
50
0
V_REF
0.9
25
0
V_REF
0.9
50
0
1.1
1.8
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL, Class II, 1.8V
SSTL, Class I, 2.5V
SSTL18_I
SSTL18_II
SSTL2_I
50
0
V_REF
0.9
25
0
V_REF
0.9
50
0
V_REF 1.25
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
26