TI380C27 Datasheet, PDF (9/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
Pin Functions (Continued)
PIN
NAME
NO.
I/O ^†
DESCRIPTION
SALE
System address-latch enable. SALE is the enable pulse used to externally latch the 16 LSBs of the
64
O
address from the SADH0 – SADH7 and SADL0 – SADL7 buses at the start of the DMA cycle. Systems
that implement address parity can also externally latch the parity bits (SPH and SPL) for the latched
address.
SBBSY
System bus busy. The TI380C27 samples the value on SBBSY during arbitration (see Note 1). The
sample has one of two values:
50
I
H = Not busy. The TI380C27 can become bus master if the grant condition is met.
L = Busy. The TI380C27 cannot become bus master.
SBCLK
System bus clock. The TI380C27 requires SBCLK to synchronize its bus timings for all DMA transfers.
65
I
Valid frequencies are 2 MHz – 33 MHz.
SBHE/SRNW
79
SBHE is used for system byte high enable. SBHE is a 3-state output driven during DMA;
it is an input at all other times.
Intel Mode
H = System byte high not enabled (see Note 1)
L = System byte high enabled
I/O
SRNW is used for system read not write. SRNW serves as a control signal to indicate
Motorola ^{a read or write cycle.}
Mode _{H = Read cycle (see Note 1)}
L = Write cycle
SBRLS
System bus release. SBRLS indicates to the TI380C27 that a higher-priority device requires the system
bus. The value on SBRLS is ignored when the TI380C27 is not perfoming DMA. SBRLS is internally
synchronized to SBCLK.
49
I
H = The TI380C27 can hold onto the system bus (see Note 1).
L = The TI380C27 should release the system bus upon completion of current DMA cycle. If the
DMA transfer is not yet complete, the SIF rearbitrates for the system bus.
System chip select. SCS activates the system interface of the TI380C27 for a DIO read or write.
SCS
48
I
H = Not selected (see Note 1)
L = Selected
SDBEN
System data-bus enable. SDBEN signals to the external data buffers to begin driving data. SDBEN is
activated during both DIO and DMA.
80
O
H = Keep external data buffers in the high-impedance state
L = Cause external data buffers to begin driving data
System data direction. SDDIR provides to the external data buffers a signal indicating the direction the
data is moving. During DIO writes and DMA reads, SDDIR is low (data direction is into the TI380C27).
During DIO reads and DMA writes, SDDIR is high (data direction is out from the TI380C27). When the
system interface is not involved in a DIO or DMA operation, SDDIR is high by default.
SDDIR
59
O
DATA
SDDIR DIRECTION DIO DMA
H
output
read write
L
input
write read
† _{I = input, O = output}
NOTE 1: Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
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