TI380C27 Datasheet, PDF (14/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
Pin Functions (Continued)
PIN
NAME
DRVR
DRVR
TXD
LPBK
TXC
RXC
RXD
CRS
COLL
Network-Media Interface — Ethernet Mode (TEST1 = L, TEST2 = H)
I/O ^†
NO.
DESCRIPTION
115
114
O
DRVR and DRVR have no Ethernet function and should be left unconnected.
Ethernet transmit data. TXD provides the Ethernet PHY-layer circuitry with a bit-rate from the
111
O
TI380C27. Data is output synchronously TXC. TXD is normally connected to TXD of an Ethernet serial
network interface (SNI) chip.
Loopback. LPBK enables loopback of Ethernet transmit data through the Ethernet (SNI) device to
receive data.
112
O
H = Wrap through the front-end device
L = Normal operation
Ethernet transmit clock. TXC is a 10-MHz clock input used to synchronize transmit data from the
118
I
TI380C27 to the Ethernet PHY layer circuitry. TXC is a continuously running clock and is normally
connected to the TXC output of an Ethernet SNI chip (see Note 5).
Ethernet receive clock. RXC is a 10-MHz clock input used to synchronize received data from the
Ethernet PHY-layer circuitry to the TI380C27. RXC must be present whenever CRS is active (although
120
I
it can be held low for a maximum of 16 clock cycles after the rising edge of CRS). When CRS is inactive,
it is permissible to hold RXC low and is normally connected to the RXC output of an Ethernet SNI chip.
The TI380C27 requires RXC to be maintained in the low state when CRS is not asserted (see Note
5).
Ethernet received data. RXD signal provides the TI380C27 with bit-rate network data from the Ethernet
121
I
front-end device. Data must be synchronous with RXC and is normally connected to RXD of an
Ethernet SNI chip (see Note 5).
Ethernet carrier sense. CRS indicates to the TI380C27 that the Ethernet PHY-layer circuitry has
network data present on RXD. CRS is asserted (high) when the first bit of the frame is received and
110
I
is deasserted after the last bit of the frame is received.
H = Receiving data
L = No data on network
Ethernet collision detect. COLL indicates to the TI380C27 that the Ethernet PHY-layer circuitry has
detected a network collision. COLL must be present for at least two TXC clock cycles to ensure it is
accepted by the TI380C27 and is normally connected to COLL of an Ethernet SNI chip. COLL can also
113
I
be an indication of the SQE test signal.
H = COLL detected by the SNI device
L = Normal operation
TXEN
Ethernet transmit enable. TXEN indicates to the Ethernet PHY-layer circuitry that bit-rate data is
present on TXD. TXEN is output synchronously to TXC and is normally connected to TXE of an
116
O
Ethernet SNI chip.
H = Data line currently contains data to be transmitted
L = No valid data on TXEN
† _{I = input, O = output}
NOTE 5: Pin has an expanded input voltage specification.
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