TI380C27 Datasheet, PDF (70/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

T4
TX
TWAIT
V
T1
T2
T3
T4
T1
SBCLK
SAS
SUDS,
SLDS
SRNW
SXAL
SALE
SADL0 – SADH7,
SADH0 – SADL7,
SPL, SPH
SDTACK
(see Notes
A and B)
SDDIR
216
Low
222
211
233a
218
211a
217
217
218
216
212
212
233
Extended Address
233
219
Address
237W
208b
223W
Output Data
208a
209
216a
221
225W
225WH
SDBEN
NOTES: E. All VSS pins should be routed to minimize inductance to system ground.
F. On a read cycle, the read strobe remains active until the internal sample of incoming data is completed. Input data can be removed when either the read strobe
or SDBEN becomes no longer active.
Figure 35. 68xxx-Mode DMA Write-Cycle Timing