TI380C27 Datasheet, PDF (56/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

SBCLK
SBHE
(see Note A)
SRD
SWR
SXAL
SALE
SADL0 –
SADH7,
SADH0 –
SADL7,
SPH, SPL
(see Note B)
SRDY
SDBEN
T4
TX
TWAIT
T1
T2
V
T3
T4
T1
212
Valid
217
216
227W
High
217
223W
216
216a
212
233
233
212
218
Address
218
219
221
Output Data
Extended Address
208a
237W
208b
225WH
225W
SDDIR
High
NOTES: A. In 8-bit 80x8x mode, SBHE/SRNW is a don’t care input during DIO and an inactive (high) output during DMA.
B. In 8-bit 80x8x mode, the most significant byte of the address is maintained on SADH for T2, T3, and T4. The address is maintained according to parameter 21;
i.e., held after T4 high.
Figure 27. 80x8x-Mode DMA Write-Cycle Timing