TI380C27 Datasheet, PDF (10/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
PIN
NAME
NO.
SHLDA/SBGR
58
SHRQ/SBRQ
78
SIACK
43
I/O ^†
I
O
I
Pin Functions (Continued)
DESCRIPTION
Intel Mode
SHLDA is used for system hold acknowledge. SHLDA indicates that the system DMA
hold request has been acknowledged. It is internally synchronized to SBCLK
(see Note 1).
H = Hold request acknowledged
L = Hold request not acknowledged
Motorola
Mode
SBGR is used for system bus grant. SBGR is an active-low bus grant, as defined in the
standard 68xxx interface, and is internally synchronized to SBCLK (see Note 1).
H = System bus not granted
L = System bus granted
Intel Mode
SHRQ is used for system hold request. SHRQ is used to request control of the system
bus in preparation for a DMA transfer. SHRQ is internally synchronized to SBCLK.
H = System bus requested
L = System bus not requested
Motorola
Mode
SBRQ is used for system bus request. SBRQ is used to request control of the system
bus in preparation for a DMA transfer. SBRQ is internally synchronized to SBCLK.
H = System bus not requested
L = System bus requested
System interrupt acknowledge. SIACK is from the host processor to acknowledge the interrupt request
from the TI380C27.
H = System interrupt not acknowledged (see Note 1)
L = System interrupt acknowledged: The TI380C27 places its interrupt vector onto the system
bus.
System Intel/Motorola mode select. The value on SI/M specifies the system-interface mode.
SI/M
56
I
H = Intel-compatible interface mode selected. Intel interface can be 8-bit or 16-bit mode
(see S8/SHALT description and Note 1).
L = Motorola-compatible interface mode selected. Motorola interface mode is always 16 bits.
SINTR/SIRQ
57
SINTR is used for system-interrupt request. TI380C27 activates SINTR to signal an
interrupt request to the host processor.
Intel Mode
H = Interrupt request by TI380C27
L = No interrupt request
O
SIRQ is used for system-interrupt request. TI380C27 activates SIRQ to signal an
Motorola ^{interrupt request to the host processor.}
Mode _{H = No interrupt request}
L = Interrupt request by TI380C27
SOWN
System bus owned. SOWN indicates to external devices that TI380C27 has control of the system bus.
SOWN drives the enable signal of the bus transceiver chips that drive the address and bus-control
81
O
signals.
H = TI380C27 does not have control of the system bus.
L = TI380C27 has control of the system bus.
SPH
84
I/O
System parity high. The optional odd-parity bit for each address or data byte transmitted over
SADH0 – SADH7 (see Note 1).
SPL
77
I/O
System parity low. The optional odd-parity bit for each address or data byte transmitted over
SADL0 – SADL7 (see Note 1).
† _{I = input, O = output}
NOTE 1: Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
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