TI380C27 Datasheet, PDF (7/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

PIN
NAME
NO.
MCAS
141
MDDIR
138
MOE
3
MRAS
143
MREF
130
MRESET
125
MROMEN
133
† _{I = input, O = output}
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
I/O ^†
O
I/O
O
O
O
O
O
Pin Functions (Continued)
SPWS014A – APRIL 1994 – REVISED MARCH 1995
DESCRIPTION
Column-address strobe for DRAMs. MCAS is valid for the 3/16 of the memory cycle following the
row-address portion of the cycle. MCAS is driven low every memory cycle while the column address
is valid on MADL0 – MADL7, MAXPH, and MAXPL, except when one of the following
conditions occurs:
1) When the address accessed is in the BIA ROM (> 00.0000 – > 00.000F)
2) When the address accessed is in the EPROM memory map (i.e., when the BOOT bit in
the SIFACL register is zero and an access is made between > 00.0010 – > 00.FFFF
or > 1F.0000 – > 1F.FFFF)
3) When the cycle is a refresh cycle, in which case MCAS is driven at the start of the cycle before
MRAS (for DRAMs that have CAS-before-RAS refresh). For DRAMs that do not support CAS-
before-RAS refresh, it may be necessary to disable MCAS with MREF during the refresh
cycle.
Data direction. MDDIR is used as a direction control for bidirectional bus drivers. This signal becomes
valid before MBEN becomes active.
H = TI380C27 memory-bus write
L = TI380C27 memory-bus read
Memory output enable. MOE is used to enable the outputs of the DRAM memory during a read cycle.
This signal is high for EPROM or BIA ROM read cycles.
H = Disable DRAM outputs
L = Enable DRAM outputs
Row-address strobe for DRAMs. The row address lasts for the first 5/16 of the memory cycle. MRAS
is driven low every memory cycle while the row address is valid on MADL0 – MADL7, MAXPH, and
MAXPL for both RAM and ROM cycles. It is also driven low during refresh cycles when the refresh
address is valid on MADL0 – MADL7.
DRAM refresh cycle in progress. MREF is used to indicate that a DRAM refresh cycle is occurring. It
is also used for disabling MCAS to all DRAMs that do not use a CAS-before-RAS refresh.
H = DRAM refresh cycle in process
L = Not a DRAM refresh cycle
Memory-bus reset. MRESET is a reset signal generated when either the ARESET bit in the SIFACL
register is set or SRESET is asserted. This signal is used for resetting external local-bus glue logic.
H = External logic not reset
L = External logic reset
ROM enable. During the first 5/16 of the memory cycle, MROMEN is used to provide a chip select for
ROMs when the BOOT bit of the SIFACL register is zero (i.e., when code is resident in ROM, not RAM).
It can be latched by MAL. It goes low for any read from addresses > 00.0010 – > 00.FFFF or > 1F.0000
– > 1F.FFFF when the BOOT bit in the SIFACL register is zero. MROMEN stays high for writes to these
addresses, accesses of other addresses, or accesses of any address when the BOOT bit is 1. During
the final three quarters of the memory cycle, MROMEN outputs the A13 address signal for interfacing
to a BIA ROM. This means MBIAEN, MAX0, ROMEN, and MAX2 together form a glueless interface
for the BIA ROM.
H = ROM disabled
L = ROM enabled
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