TI380C27 Datasheet, PDF (54/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TWAIT
T4
TX
T1
T2
V
T3
T4
T1
SBCLK
SRAS
SBHE
(see Note A)
SWR
SRD
(see Note B)
SXAL
SALE
SADH0 – SADH7,
SADL0 – SADL7,
SPH, SPL
(see Note C)
SRDY
216
217
216
233
212
218
Extended
Address
212
227R
218
217
Hi-Z
High
Valid
226
212
214
233
Address
218
205
Data
247
208a
(see Note D)
223R
216a
207a
206
207b
229
Address
SDBEN
(see Note B)
237R
208b
225R
SDDIR
Low
NOTES: A. In 8-bit 80x8x mode, SBHE/SRNW is a don’t care input during DIO and an inactive (high) output during DMA.
B. Motorola-style bus slaves hold SDTACK active until the bus master deasserts SAS.
C. In 8-bit 80x8x mode, the most significant byte of the address is maintained on SADH for T2, T3, and T4. The address is maintained according to parameter 21; i.e., held
after T4 high.
D. If parameter 208a is not met, valid data must be present before SRDY goes low.
Figure 26. 80x8x-Mode DMA Read-Cycle Timing