TI380C27 Datasheet, PDF (18/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
system interface (SIF) (continued)
When the TI380C27 enters the slow-clock mode, the clock that failed is replaced by a slow free-running clock
and the device is placed into a low-power reset state. When the failed clock(s) return to valid operation, the
TI380C27 must be reinitialized.
For DMA with a 16-MHz clock, a continuous transfer rate of 64 megabits per second (8 Mbps) can be obtained.
For DMA with a 25-MHz clock, a continuous transfer rate of 96 megabits per second (12 Mbps) can be obtained.
For DMA with a 33 MHz clock, a continuous transfer rate of 128 megabits per second ( 16 Mbps ) can be
obtained.For 8-bit and 16-bit pseudo-DMA, the following data rates can be obtained:
LOCAL BUS SPEED
4 MHz
6 MHz
8-BIT PDMA
48 Mbps
72 Mbps
16-BIT PDMA
64 Mbps
96 Mbps
Since the main purpose of DIO is for downloading and initialization, the DIO transfer rate is not a significant
issue.
memory interface (MIF)
The MIF performs the memory management to allow the TI380C27 to address 2M bytes in local memory.
Hardware in the MIF allows the TI380C27 to be directly connected to DRAMs without additional circuitry. This
glueless DRAM connection includes the DRAM refresh controller. The MIF also handles all internal bus
arbitration between these blocks. When required, the MIF then arbitrates for the external bus.
The MIF is responsible for the memory mapping of the CPU of a task. The memory map of DRAMs, EPROMs,
burned-in addresses (BIA), and external devices are appropriately addressed when required by the system
interface, protocol handler, or for a DMA transfer.
The memory interface is capable of a 64-Mbps continuous transfer rate when using a 4-MHz local bus ( 64-MHz
device crystal ) and a 96-Mbps continuous transfer rate when using a 6-MHz local bus.
protocol handler (PH)
The PH performs the hardware-based real-time protocol functions for a token-ring or an Ethernet LAN. Network
type is determined by TEST0 – TEST2. Token-ring network is determined by software and can be either 16 Mbps
or 4 Mbps. The Ethernet network can be either full duplex or half duplex. These speeds are not fixed by the
hardware but by the software.
The PH converts the parallel-transmit data to serial-network data of the appropriate coding and converts the
received serial data to parallel data. The PH data-management state machines direct the
transmission/reception of data to / from local memory through the MIF. The PH’s buffer-management state
machines automatically oversee this process, directly sending/receiving linked lists of frames without CPU
intervention.
The protocol handler contains many state machines that provide the following features:
• Transmit and receive frames
• Capture tokens (token ring)
• Provide token-priority controls (token ring)
• Automatic retry of frame transmissions after collisions ( Ethernet)
• Implement the random exponential backoff algorithm ( Ethernet)
• Manage the TI380C27 buffer memory
• Provide frame-address recognition (group, specific, functional, and multicast)
• Provide internal parity protection
• Control and verify the PHY-layer circuitry-interface signals
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