TI380C27 Datasheet, PDF (31/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
VDD
SBCLK
OSCIN
MBCLK1
MBCLK2
100
101
102
SPWS014A – APRIL 1994 – REVISED MARCH 1995
Minimum VDD-High Level
103
106
106
104
105
107
108
110
110
109
111
SRESET
S8/SHALT
117
288
118
119
289
NOTE A: In order to represent the information is one illustration, nonactual phase and timebase characteristics are shown. Refer to specified
parameters for precise information.
Figure 4. Timing for Power Up, System Clocks, SYNCIN, and SRESET
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