TI380C27 Datasheet, PDF (6/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
Pin Functions (Continued)
PIN
NAME
NO.
MAX2
140
I/O ^†
I/O
DESCRIPTION
Local-memory-extended address bit. MAX2 drives AX2 at row-address time, which can be latched by
MRAS, and drives A14 at column-address and data-valid times for all cycles. Driving A14 eases
interfacing to a BIA ROM.
Memory Cycle
1Q
2Q
3Q
4Q
Signal
AX2
A14
A14
A14
MAXPH
Local-memory-extended address and parity — high byte. For the first quarter of a memory cycle,
MAXPH carries the extended-address bit AX1; for the second quarter of a memory cycle, it carries the
extended-address bit AX0; and for the last half of the memory cycle, it carries the parity bit for the
16
I/O
high-data byte.
Memory Cycle
1Q
2Q
3Q
4Q
Signal
AX1
AX0
Parity
Parity
MAXPL
Local-memory-extended address and parity — low byte. For the first quarter of a memory cycle,
MAXPL carries the extended-address bit AX3; for the second quarter of a memory cycle, it carries
extended-address bit AX2; and for the last half of the memory cycle, it carries the parity bit for the
20
I/O
low-data byte.
Memory Cycle
1Q
2Q
3Q
4Q
Signal
AX3
AX2
Parity
Parity
Local-bus clock 1 and local-bus clock 2. These signals are referenced for all local-bus transfers.
MBCLK2 lags MBCLK1 by a quarter of a cycle. These clocks operate according to:
MBCLK1
MBCLK2
123
124
O
MBCLK[1:2]
8 MHz
8 MHz
12 MHz
OSCIN
64 MHz
32 MHz
48 MHz
CLKDIV
H
L
L
MBEN
Buffer enable. MBEN enables the bidirectional buffer outputs on the MADH, MAXPH, MAXPL, and
MADL buses during the data phase. This signal is used in conjunction with MDDIR, which selects the
4
O
buffer output direction.
H = Buffer output disabled
L = Buffer output enabled
MBGR
18
I/O
Reserved; must be left unconnected.
Burned-in address enable. MBIAEN is an output signal used to provide an output enable for the ROM
containing the adapter’s burned-in address (BIA).
MBIAEN
127
O
H = This signal is driven high for any write accesses to the addresses between > 00.0000 and
> 00.000F, or any accesses (read/write) to any other address.
L = This signal is driven low for any read from addresses between > 00.0000 and > 00.000F.
MBRQ
17
I/O
Reserved; must be pulled high (see Note 3).
† _{I = input, O = output}
NOTE 3: Each pin must be individually tied to VCC with a 1-kΩ pullup resistor.
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