TI380C27 Datasheet, PDF (58/77 Pages) Texas Instruments – DUAL-PROTOCOL COMMPROCESSOR

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
80x8x-mode bus-release timing
NO.
208a
Setup time, asynchronous input SBRLS low before SBCLK no longer high to assure
recognition
208b Hold time, asynchronous input SBRLS low after SBCLK low to assure recognition
208c Hold time, SBRLS low after SOWN high
25-MHz
OPERATION
MIN MAX
33-MHz
OPERATION
MIN MAX
10
10
10
10
0
0
UNIT
ns
ns
ns
T(W or 2)
T3
T4
T1
T2
SBCLK
SBRLS
(see Note A)
208a
208b
SOWN
208c
NOTES: A. The system interface ignores the assertion of SBRLS if it does not own the system bus. If it does own the bus when it detects the
assertion of SBRLS, it completes any internally started DMA cycle and relinquishes control of the bus. If no DMA transfer has
internally started, the system interface releases the bus before starting another.
B. If SBERR is asserted when the system interface controls the system bus, the current bus transfer is completed regardless of the
value of SRDY. If the BERETRY register is non zero, the cycle is retried. If the BERETRY register is zero, the system interface
releases control of the system bus. The system interface ignores the assertion of SBERR if it is not performing a DMA bus cycle
on the system bus. When SBERR is properly asserted and BERETRY is zero, however, the system interface releases the bus upon
completion of the current bus transfer and halts all further DMA on the system side. The error is synchronized to the local bus and
DMA stops on the local sides. The value of the SDMAADR, SDMADDRX, and SDMALEN registers in the system interface are not
defined after a system-bus error.
C. In cycle-steal mode, state TX is present on every system bus transfer. In burst mode, state TX is present on the first bus transfer
and whenever the increment of the DMA address register carries beyond the least significant 16 bits.
D. SDTACK is not sampled to verify that it is deasserted.
E. Unless otherwise specified, for all signals specified as a maximum delay from the end of an SBCLK transition to the signal valid,
the signal is also specified to hold its previous value (including high impedance) until the start of that SBCLK transition.
Figure 29. 80x8x-Mode Bus-Release Timing
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